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74HC4053D-Q100

Description
SGL ENDED MULTIPLEXER
Categorysemiconductor    Analog mixed-signal IC   
File Size330KB,30 Pages
ManufacturerNXP
Websitehttps://www.nxp.com
Download Datasheet Parametric Compare View All

74HC4053D-Q100 Overview

SGL ENDED MULTIPLEXER

74HC4053D-Q100 Parametric

Parameter NameAttribute value
Lead-freeYes
EU RoHS regulationsYes
China RoHS regulationsYes
stateACTIVE
terminal coatingNOT SPECIFIED
Analog IC other typesSGL ENDED MULTIPLEXER
74HC4053-Q100; 74HCT4053-Q100
Triple 2-channel analog multiplexer/demultiplexer
Rev. 2 — 22 November 2012
Product data sheet
1. General description
The 74HC4053-Q100; 74HCT4053-Q100 is a high-speed Si-gate CMOS device and is pin
compatible with Low-power Schottky TTL (LSTTL). It is specified in compliance with
JEDEC standard no. 7A.
The 74HC4053-Q100; 74HCT4053-Q100 is triple 2-channel analog
multiplexer/demultiplexer with a common enable input (E). Each multiplexer/demultiplexer
has two independent inputs/outputs (nY0 and nY1), a common input/output (nZ) and three
digital select inputs (Sn). With E LOW, one of the two switches is selected
(low-impedance ON-state) by S1 to S3. With E HIGH, all switches are in the
high-impedance OFF-state, independent of S1 to S3.
V
CC
and GND are the supply voltage pins for the digital control inputs (S0 to S2, and E).
The V
CC
to GND ranges are 2.0 V to 10.0 V for 74HC4053-Q100, and 4.5 V to 5.5 V for
74HCT4053-Q100. The analog inputs/outputs (nY0 to nY1, and nZ) can swing between
V
CC
as a positive limit and V
EE
as a negative limit. V
CC
V
EE
may not exceed 10.0 V.
For operation as a digital multiplexer/demultiplexer, V
EE
is connected to GND (typically
ground).
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
Wide analog input voltage range from
5
V to +5 V
Low ON resistance:
80
(typical) at V
CC
V
EE
= 4.5 V
70
(typical) at V
CC
V
EE
= 6.0 V
60
(typical) at V
CC
V
EE
= 9.0 V
Logic level translation: to enable 5 V logic to communicate with
5
V analog signals
Typical ‘break before make’ built-in
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
CDM AEC-Q100-011 revision B exceeds 1000 V
Multiple package options

74HC4053D-Q100 Related Products

74HC4053D-Q100 74HC4053-Q100 74HC4053BQ-Q100 74HC4053PW-Q100 74HCT4053-Q100 74HCT4053BQ-Q100 74HCT4053D-Q100 74HCT4053PW-Q100
Description SGL ENDED MULTIPLEXER SGL ENDED MULTIPLEXER SGL ENDED MULTIPLEXER SGL ENDED MULTIPLEXER SGL ENDED MULTIPLEXER SGL ENDED MULTIPLEXER SGL ENDED MULTIPLEXER SGL ENDED MULTIPLEXER
Is it Rohs certified? - - conform to conform to - conform to conform to conform to
Maker - - NXP NXP - NXP NXP NXP
Reach Compliance Code - - unknown unknown - unknown unknown unknown
Analog Integrated Circuits - Other Types - - SINGLE-ENDED MULTIPLEXER SINGLE-ENDED MULTIPLEXER - SINGLE-ENDED MULTIPLEXER SINGLE-ENDED MULTIPLEXER SINGLE-ENDED MULTIPLEXER
Humidity sensitivity level - - 1 1 - 1 1 1
Peak Reflow Temperature (Celsius) - - 260 260 - 260 260 260
Maximum time at peak reflow temperature - - 30 30 - 30 30 30
Base Number Matches - - 1 1 - 1 1 1

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