FEDL9480-01
Issue Date:
Oct. 1, 2012
ML9480
Static, 1/2 Duty, 1/3 Duty, 1/4 Duty 40 Outputs LCD Driver
GENERAL DESCRIPTION
The ML9480 is an LCD driver LSI, consists of a 40-bit shift register, a 160-bit data latch, 40 sets of LCD drivers,
and a common signal generation circuit.
It can directly drive an LCD up to 40 segments for static display, 80 segments for 1/2-duty display, 120
segments for 1/3-duty display, and 160 segments for 1/4-duty display.
The three-wire serial interface and I
2
C interface are selectable.
FEATURES
Logic power supply voltage
: 2.7 to 5.5 V
LCD drive power supply voltage : 4.5 to 5.5 V
Maximum number of segments
Static display
: 40 segments
1/2-duty display
: 80 segments
1/3-duty display
: 120 segments
1/4-duty display
: 160 segments
Interface with microcomputer :
Serial interface : DATA, CLOCK, LOAD
CLOCK transfer speed up to 1 MHz
2
: SDA, SCL, SDAACK
I C interface
SCL transfer speed up to 400 kHz
Built-in CR oscillator circuit using the internal resistor or External resistor
Cascade connectable (up to sixteen chips)
Built-in common signal generation circuit
Built-in common output intermediate-value voltage generation circuit
Built-in POC (Power On Clear) circuit
Gold bump chip (ML9480DVWA)
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BLOCK DIAGRAM
SEG1
VLCD
SEG40
BIAS
Bias
Resi.
40-Dot Segment Driver
40-Ch Data Selector
Duty0
Duty1
40
40-Bit
Latch4
40
40-Bit
Latch3
40
40-Bit
Latch2
40
40-Bit
Latch1
M/S
LATCH
SELECTOR
MODE
I2C
LOAD
DATA（SDA）
CLOCK（SCL）
SDAACK
SA1
SA0
A1
A0
OSC I/E
OSC1
OSCR
OSC2
CKO
SYNCB
POCEB
RESETB
POC
Circuit
TIMING
GENERATOR
COMMON
Driver
COM1
COM2
COM3
COM4
OSC
Command
Decoder
40-bit Shift Register
40
TEST1
VDD
GND
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ABSOLUTE MAXIMUM RATINGS
Item
Logic power supply voltage
LCD drive power supply voltage
Input voltage
Output short-circuit current
Chip temperature
Storage temperature
Symbol
V
DD
V
LCD
V
I
Is
Tc
T
STG
Condition
Ta = 25°C
Ta = 25°C
Ta = 25°C
Ta = 25°C
—
—
Rating
-0.3 to 6.0
-0.3
to 6.0
– 0.3 to V
DD
+ 0.3
-2.0
to +2.0
125
-55 to +150
Unit
V
V
V
mA
°C
°C
Note: Do not use the ML9480 by short-circuiting one output pin to another output pin as well as to other pin
(input pin, input/output pin, or power supply pin).
RECOMMENDED OPERATION CONDITIONS
Item
Logic power supply voltage
LCD drive power supply voltage
OSC IN clock frequency
Data clock frequency
SCL clock frequency
Operating temperature
Symbol
V
DD
*
V
LCD
*
f
CP1
f
CP2
f
SCL
T
a
Condition
—
—
—
—
—
—
Range
2.7 to 5.5
4.5 to 5.5
up to 10
up to 1.0
up to 400
-40 to +105
Unit
V
V
kHz
MHz
kHz
°C
Note(*): Use at V
DD
V
LCD
.
The relation between OSC IN clock frequency and frame frequency is as the equation below.
f
FRM
= f
OSC
/24
Recommended setting range for external component (oscillator circuit)
Item
Oscillation resistor
Frame frequency
Symbol
R
f
f
FRM
Condition
—
(F1,F0)=(0,1)
(V
DD
= 2.7 to 5.5 V, V
LCD
= 4.5 to 5.5 V, Ta= –40 to +105°C)
Min
TYP
Max
Unit
423
47
470
75
517
114
kΩ
Hz
The relation between oscillation resistor and frame frequency is as the equation below.
f
FRM
= f
OSC
/(16 x 24)
fosc = 1 / (Device coefficient x External resistor R
f
)
Device coefficient = 73.8 x 10
-12
± 25%
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ELECTRICAL CHARACTERISTICS
DC Characteristics
Item
"H" input voltage
"L" input voltage
Input leakage current 1
Input leakage current 2
Pull-up current
"H" output voltage
"L" output voltage 1
"L" output voltage 2
Driver
ON resistor
Segment
Common
Symbol
V
IH
V
IL
I
L1
I
L2
I
pu
V
OH
V
OL1
V
OL2
V
OHS
V
OHC
(V
DD
= 2.7 to 5.5 V, V
LCD
= 4.5 to 5.5 V, Ta= -40 to +105°C)
Condition
Min.
Typ.
Max.
Unit
Applicable pin
—
0.8V
DD
—
V
DD
V
(*1)
—
GND
—
0.2V
DD
V
(*1)
V
I
= V
DD
or 0 V
-1.0
—
1.0
A
(*1)
V
I
= V
DD
or 0V
-1.0
—
1.0
A
RESETB
POCEB="H"
V
DD
= 5.0V,V
I
= 0 V
30
—
140
A
RESETB
POCEB = "L"
I
O
= -600uA
0.9V
DD
—
—
V CKO, SYNCB
I
O
= 600uA
—
—
0.1V
DD
V
CKO, SYNCB
VDD=5V,
3
—
—
mA SDAACK
V
OL
= 0.4V
V
LCD
= 5V
V
LCD
= 5V
—
—
5
5
15
12
kΩ
kΩ
SEG1 to SEG40
COM 1 to COM4
(*1) : DATA(SDA), CLOCK(SCL), LOAD, M/S, SYNCB, Duty1, Duty0, BIAS, SA1,SA0, A1, A0, OSC1,
OSC I/E, I2C, POCEB, MODE
Item
Static supply
current
Dynamic supply
current 1
Dynamic supply
current 2
Dynamic supply
current 3
Dynamic supply
current 4
Symbol
I
DDS
I
LCDS
I
DD1
I
LCD1
I
DD2
I
LCD2
I
DD3
I
LCD3
I
DD4
I
LCD4
Condition
(V
DD
= 2.7 to 5.5 V, V
LCD
= 4.5 to 5.5 V, Ta= -40 to +105°C)
Applicable
Min.
Typ.
Max.
Unit
pin
—
—
—
—
—
—
—
—
—
—
8
9
10
9
59
9
100
9
188
9
15
15
18
13
90
15
200
15
310
15
A
A
A
A
A
A
A
A
A
A
VDD
VLCD
VDD
VLCD
VDD
VLCD
VDD
VLCD
VDD
VLCD
V
DD
=V
LCD
=5.5 V
Input pin fixed to "H" or "L"
Oscillation stopped, output no-load
POCEB="L"
V
DD
=V
LCD
= 5.5 V (*2)(*3)
(*6)
Clock OSC1 external input
(*7)
f
CP1
=1.8kHz
V
DD
=V
LCD
= 5.5 V (*2)(*3)
Internal oscillation
(*6)
(*7)
V
DD
=V
LCD
= 5.5 V (*2)(*4)(*6)
Internal oscillation
At three-wire serial IF data input
V
DD
=V
LCD
= 5.5 V (*2)(*5)(*6)
Internal oscillation
2
At I C IF data input
(*2) : M/S = "H", 1/4-duty, 1/3-bias, (F1,F0,FSEL) = (1,1,0) 95 Hz, POCEB = "L", output pin no-load.
(*3) : Three-wire serial or I
2
C interface. Input pin fixed to "H" or "L".
(*4) : Serial interface, data input frequency = 1 MHz.
(*5) : I
2
C interface, data input frequency = 400 kHz.
(*6) : Alternately inputs "0" and "1" for LCD display data (checkered display).
(*7) : Inputs all "1s" for LCD display data (all illuminated).
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Switching Characteristics
OSC timing
Symbol
f
CP1
t
WCP1
t
OSC
Between OSC1 and OSC2
R
f
= 470kΩ
(F1,F0)=(0,1)
OSCR open.
OSC I/E = "H"
OSC1 open.
(F1,F0)=(0,1)
OSC2 and OSCR short-circuited.
OSC I/E = "H"
Clock input from OSC1.
OSC2 and OSCR open.
OSC I/E = "L"
(V
DD
= 2.7 to 5.5 V, V
LCD
= 4.5 to 5.5 V, Ta = -40 to +105°C)
Condition
Min.
Typ. Max.
Unit
Applicable pin
—
40
—
1.8
—
—
10
—
(*1)
kHz
s
s
OSC1
OSC1
OSC1
Item
OSC IN clock frequency
(external input)
Clock pulse width
(External input)
Clock rise and fall time
(external input)
External Rf clock
frequency
(Internal oscillation)
f
OSC1
18
28.8
44
kHz
OSC1, OSC2
Internal clock frequency
(Internal oscillation)
f
OSC2
18
28.8
44
kHz
OSC1, OSCR,
OSC2
The relation between OSC IN clock frequency and frame frequency is as the equation below.
f
FRM
= f
OSC
/24
(*1) t
OSC
is a reference value.
The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value.
Make the rise as steep as possible. Reference value: max=2s.
Serial interface timing
Symbol
f
CP2
t
WCP2
t
SU
t
HD
t
CL
t
LC
t
WLD
tsr,tsf
(V
DD
= 2.7 to 5.5 V, V
LCD
= 4.5 to 5.5 V, Ta = -40 to +105°C)
Condition
Min. Typ. Max. Unit
Applicable pin
—
—
1
MHz CLOCK
100
—
—
ns CLOCK
50
—
—
ns DATA
50
—
—
ns CLOCK
100
—
—
ns CLOCK
100
—
—
ns LOAD
100
—
—
ns LOAD
CLOCK,DATA,
—
—
(*2)
ns
LOAD
Item
Data clock frequency
Data clock pulse width
Data setup time
Data hold time
CLOCK-LOAD timing
LOAD-CLOCK timing
LOAD pulse width
Signal rise and fall time
(*2) tsr and tsf shall be reference values.
The longer the clock rise and fall time, the more susceptible to extraneous noises around the threshold value.
Make the rise as steep as possible. Reference value: max=10ns.
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