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2309G-1HLF

Description
PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, 0.65 MM PITCH, GREEN, TSSOP-16
Categorylogic    logic   
File Size157KB,10 Pages
ManufacturerIDT (Integrated Device Technology)
Environmental Compliance
Download Datasheet Parametric View All

2309G-1HLF Overview

PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, 0.65 MM PITCH, GREEN, TSSOP-16

2309G-1HLF Parametric

Parameter NameAttribute value
Is it lead-free?Lead free
Is it Rohs certified?conform to
Parts packaging codeTSSOP
package instructionTSSOP, TSSOP16,.25
Contacts16
Reach Compliance Codecompli
series2309
Input adjustmentSTANDARD
JESD-30 codeR-PDSO-G16
JESD-609 codee3
length5 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
Humidity sensitivity level1
Number of functions1
Number of inverted outputs
Number of terminals16
Actual output times8
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeTSSOP
Encapsulate equivalent codeTSSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, THIN PROFILE, SHRINK PITCH
Peak Reflow Temperature (Celsius)260
power supply3.3 V
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.25 ns
Maximum seat height1.2 mm
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceMatte Tin (Sn) - annealed
Terminal formGULL WING
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width4.4 mm
minfmax133 MHz
Base Number Matches1
DATASHEET
3.3 VOLT ZERO DELAY LOW SKEW BUFFER
Description
The ICS2309 is a low phase noise, high-speed PLL
based, low-skew zero delay buffer. Based on ICS’
proprietary low jitter Phase Locked Loop (PLL)
techniques, the device provides nine low skew outputs
at speeds up to 133 MHz at 3.3 V. The outputs can be
generated from the PLL (for zero delay), or directly from
the input (for testing), and can be set to tri-state mode
or to stop at a low level. The PLL feedback is on-chip
and is obtained from the CLKOUT pad.
The ICS2309 is available in two different versions. The
ICS2309-1 is the base part. The ICS2309-1H is a high
drive version with faster rise and fall times.
ICS2309
Features
Clock outputs from 10 to 133 MHz
Zero input-output delay
Nine low skew (<250 ps) outputs
Device-to-device skew <700 ps
Full CMOS outputs with 12 mA output drive
capability at TTL levels
5 V tolerant CLKIN
Tri-state mode for board-level testing
Advanced, low power, sub-micron CMOS process
Operating voltage of 3.3 V
Industrial temperature range available
Packaged in 16-pin SOIC and TSSOP (-1H version
only)
complaint packaging
RoHS 5 (green) or RoHS 6 (green and lead free)
Block Diagram
VDD
2
CLKIN
PLL
0
CLKOUT
1
CLKA1
CLKA2
CLKA3
CLKA4
S2, S1 2
Control
Logic
CLKB1
CLKB2
CLKB3
CLKB4
GND
2
IDT™ / ICS™
3.3 VOLT ZERO DELAY LOW SKEW BUFFER
1
ICS2309
REV F 041906

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