Enhanced
Features
Memory Systems Inc.
DM2M36SJ6/DM2M32SJ6 Multibank EDO
2Mbx36/2Mbx32 Enhanced DRAM SIMM
Product Specification
Architecture
The DM2M36SJ6 achieves
2Mb x 36 density by mounting
18 1Mb x 4 EDRAMs, packaged
in 28-pin plastic SOJ packages,
on both sides of the multi-layer
substrate. Sixteen DM2242 and
two DM2252 devices provide
data and parity storage. The
DM2M32SJ6 contains 16
DM2242 devices for data only.
The EDRAM memory
module architecture is very
similar to a standard 8MB
DRAM module with the addition
of an integrated cache and on-
chip control which allows it to
s
16KByte SRAM Cache Memory for 12ns Random Reads Within Eight
Active Pages (Multibank Cache)
s
Fast DRAM Array for 30ns Access to Any New Page
s
Write Posting Register for 12ns Random Writes and Burst Writes
Within a Page (Hit or Miss)
s
2KByte Wide DRAM to SRAM Bus for 113.6 Gigabytes/Sec Cache Fill
s
On-chip Cache Hit/Miss Comparators Maintain Cache Coherency on Writes
s
Hidden Precharge and Refresh Cycles
s
Extended 64ms Refresh Period for Low Standby Power
s
Standard CMOS/TTL Compatible I/O Levels and +5 or 3.3V Volt Supply
s
Compatibility with JEDEC 2M x 36 DRAM SIMM Configuration
Allows Performance Upgrade in System
s
Multibank Extended Data Output (EDO) for Faster System Operation
s
Low Power, Self Refresh Option
s
Industrial Temperature Range Option
operate much like an EDO DRAM.
The Enhanced Memory Systems Multibank EDO 8MB EDRAM
The EDRAM’s SRAM cache is integrated into the DRAM array as
SIMM module provides a single memory module solution for the main tightly coupled row registers. Each EDRAM Bank has a total of four
memory or local memory of fast PCs, workstations, servers, and other independent DRAM memory banks each with its own SRAM row
high performance systems. Due to its fast 12ns cache row register,
register. Memory reads always occur from the cache row register of
the EDRAM memory module supports zero-wait-state burst read
one of these banks as specified by row address bits A
2
and A
9
(bank
operations at up to 83MHz bus rates in a non-interleave configuration select). When the internal comparator detects that the row address
and >132MHz bus rates with a two-way interleave configuration.
matches the last row read from any of the four DRAM banks (page
On-chip write posting and fast page mode operation supports
hit), the SRAM is accessed and data is available on the output pins in
12ns write and burst write operations. On a cache miss, the fast
12ns from the column address input. Subsequent reads within the
DRAM array reloads the 2KByte cache over a 2KByte-wide bus in
page (burst reads or random reads) can continue at 12ns cycle
18ns for an effective bandwidth of 113.6 Gbytes/sec. This means
time. When the row address does not match the last row read from
very low latency and fewer wait states on a cache miss than a non-
any of the last four DRAM banks (page miss), the new DRAM row is
integrated cache/DRAM solution. The JEDEC compatible 72-bit
SIMM configuration allows a single memory controller to be designed to accessed and loaded into the appropriate SRAM row register and
support either JEDEC slow DRAMs or high speed EDRAMs to provide a data is available on the output pins all within 30ns from row enable.
Subsequent reads within the page (burst reads or random reads)
simple upgrade path to higher system performance.
can continue at 12ns cycle time.
Since reads occur from the SRAM
Functional Diagram
cache, the DRAM precharge can occur
A
0-8
Column
/CAL
0-3,P
Add
Column Decoder
during burst reads. This eliminates the
Latch
4 - 512 x 36 Cache Pages
precharge time delay suffered by other
(Row Registers) x 2
8-Bit
DRAMs and SDRAMs when accessing a
Comp
new page. The EDRAM has an
Sense Amps
/G
& Column Write Select
independent on-chip refresh counter and
I/O
8 Last
Control
A
0-10
dedicated refresh control pin to allow the
Row
DQ
0-35
and
Read
Data
DRAM array to be refreshed concurrently
Add
Latches
Latch
/S
with cache read operations (hidden
0, 1
Memory
Row
refresh).
Array
/WE
Add
2048 x 512 x 36 x 2
Memory writes are posted to the
Latch
input data latch and directed to the DRAM
array. During a write hit, the on-chip
address comparator activates a parallel
V
A
0-9
C
write path to the SRAM cache to maintain
/F
Row Add
V
Row Decoder
CC
1-18
Description
W/R
/RE
0,2,3
and
Refresh
Control
Refresh
Counter
SS
The information contained herein is subject to change without notice.
Enhanced reserves the right to change or discontinue this product without notice.
© 1996 Enhanced Memory Systems Inc.,
1850 Ramtron Drive, Colorado Springs, CO
Telephone
(800) 545-DRAM;
Fax
(719) 488-9095; http://www.csn.net/ramtron/enhanced
80921
38-2119-000
coherency. Random or page mode writes can be posted 5ns after
column address and data are available. The EDRAM allows 12ns
page mode cycle time for both write hits and write misses. Memory
writes do not affect the contents of the cache row register except
during a cache hit.
By integrating the SRAM cache as row registers in the DRAM
array and keeping the on-chip control simple, the EDRAM is able
to provide superior performance over standard slow DRAMs. By
eliminating the need for SRAMs and cache controllers, system cost,
board space, and power can all be reduced.
EDRAM Basic Operating Modes
The EDRAM operating modes are specified in the table.
Functional Description
The EDRAM is designed to provide optimum memory
performance with high speed microprocessors. As a result, it is
possible to perform simultaneous operations to the DRAM and
SRAM cache sections of the EDRAM. This feature allows the EDRAM
to hide precharge and refresh operation during SRAM cache reads
and maximize SRAM cache hit rate by maintaining valid cache
contents during write operations even if data is written to another
memory page. These new functions, in conjunction with the faster
basic DRAM and cache speeds of the EDRAM, minimize processor
wait states.
Hit and Miss Terminology
In this datasheet, “hit” and “miss” always refer to a hit or miss
to any of the four pages of data contained in the SRAM cache row
registers. There are four cache row registers, one for each of the
four banks of DRAM. These registers are specified by the bank
select row address bits A
2
and A
9
. The contents of these cache row
registers is always equal to the last row that was read from each of
the four internal DRAM banks (as modified by any write hit data).
Bank Selection
The 8MByte EDRAM SIMM has two separate 4MByte banks on
one module. The two banks share common data, multiplexed
address, and control signals with the exception of /RE and /S. Bank
selection is performed by using both /RE and /S to select a bank.
The use of /S to select a bank is
required
on the 8MByte SIMM
because /G is common between the two banks. If /S is grounded
(i.e., not used to control bank selection), an output buffer conflict
between the two banks
will
occur when /G is enabled. It is also
necessary to clock the /RE signal for each bank separately since
clocking /RE with /S disabled is
not
allowed (see “Unallowed
Mode” description).
Four Bank Cache Architecture (One of Two Banks)
Bank 3
Bank 2
Bank 1
Bank 0
Row Address Latch
Last
Row
Read
Address
Latch
+ 9-Bit
Compare
RA
0-10
Column Address Latch
CA
0-8
1MB Array
1MB Array
1MB Array
1MB Array
D
0-35
A
0-10
Data-In
Latch
512 x 36
Cache
Bank 0
CA
0-8
512 x 36
Cache
Bank 1
512 x 36
Cache
Bank 2
512 x 36
Cache
Bank 3
(0,0)
RA
2
, RA
9
(0,1)
(1,0)
(1,1)
1 of 4 Selector
CAL
Data-Out
Latch
G
S
Q
0-35
2-96
DRAM Read Hit
A DRAM read request is initiated by clocking /RE with W/R low
and /F and /CAL high. The EDRAM will compare the new row
address to the last row read address latch for the bank specified by
row address A
2, 9
(LRR; an 9-bit latch loaded on each /RE active read
cycle). If the row address matches the LRR, the requested data is
already in the SRAM cache and no DRAM memory reference is
initiated. The data specified by the column address is available at the
output pins at the greater of times t
RAC1,
t
AC,
t
GQV,
and t
ASC
+ t
CLV
.
Since no DRAM activity is initiated, /RE can be brought high after
time t
RE1
, and a shorter precharge time, t
RP1
, is required. It is
possible to access additional SRAM cache locations by providing
new column addresses to the multiplex address inputs. New data is
available at the output at time t
ASC +
t
CLV
after each column address
change.
DRAM Read Miss
A DRAM read request is initiated by clocking /RE with W/R low
and /F. The EDRAM will compare the new row address to the LRR
address latch for the bank specified by row address bits A
2, 9
(LRR:
9-bit row address latch for each internal DRAM bank which is
reloaded on each /RE active read miss cycle). If the row address
does not match the LRR, the requested data is not in SRAM cache
and a new row must be fetched from the DRAM. The EDRAM will
load the new row data into the SRAM cache and update the LRR
latch. The data at the specified column address is available at the
output pins at the greater of times t
RAC,
t
AC,
t
GQV,
and t
ASC
+ t
CLV
. It is
possible to bring /RE high after time t
RE
since the new row data is
safely latched into SRAM cache. This allows the EDRAM to
precharge the DRAM array while data is accessed from SRAM cache.
It is possible to access additional SRAM cache locations by
providing new column addresses to the multiplex address inputs.
New data is available at the output at time t
ASC +
t
CLV
after each
column address change.
in the appropriate bank and its corresponding SRAM cache
simultaneously to maintain coherency. The write address and data are
posted to the DRAM as soon as the column address is latched by
bringing /CAL low and the write data is latched by bringing /WE low
(both /CAL and /WE must be high when initiating the write cycle with
the falling edge of /RE). The write address and data can be latched
very quickly after the fall of /RE (t
RAH
+ t
ASC
for the column address
and t
DS
for the data). During a write burst sequence, the second write
data can be posted at time t
RSW
after /RE. Subsequent writes within a
page can occur with write cycle time t
PC
. With /G enabled and /WE
disabled, it is possible to perform cache read operations while the /RE
is activated in write hit mode. This allows read-modify-write, write-
verify, or random read-write sequences within the page with 12ns
cycle times (the first read cannot complete until after time t
RAC2
). At
the end of a write sequence (after /CAL and /WE are brought high and
t
RE
is satisfied), /RE can be brought high to precharge the memory. It
is possible to perform cache reads concurrently with precharge.
During write sequences, a write operation is not performed unless
both /CAL and /WE are low. As a result, the /CAL input can be used as
a byte write select in multi-chip systems. If /CAL is not clocked on a
write sequence, the memory will perform a /RE only refresh to the
selected row and data will remain unmodified.
DRAM Write Miss
A DRAM write request is initiated by clocking /RE while W/R,
W/E, and /F are high. The EDRAM will compare the new row address
to the LRR address latch for the bank specified for row address bits A
2, 9
(LRR: a 9-bit row address latch for each internal DRAM bank which is
reloaded on each /RE active read miss cycle). If the row address does
not match any of the LRRs, the EDRAM will write data to the DRAM
page in the appropriate bank and the contents of the current cache is
not modified. The write address and data are posted to the DRAM as
soon as the column address is latched by bringing /CAL low and the
write data is latched by bringing /WE low (both /CAL and /WE must be
high when initiating the write cycle with the falling edge of /RE). The
DRAM Write Hit
write address and data can be latched very quickly after the fall of /RE
A DRAM write request is initiated by clocking /RE while W/R, W/E, (t
RAH
+ t
ASC
for the column address and t
DS
for the data). During a
and /F are high. The EDRAM will compare the new row address to the write burst sequence, the second write data can be posted at time t
RSW
LRR address latch for the bank specified by row address bits A
2, 9
(LRR: after /RE. Subsequent writes within a page can occur with write cycle
a 9-bit row address latch for each internal DRAM bank which is
time t
PC
. During a write miss sequence, cache reads are inhibited and
reloaded on each /RE active read miss cycle). If the row address
the output buffers are disabled (independently of /G) until time t
WRR
matches the LRR, the EDRAM will write data to both the DRAM page
after /RE goes high. At the end of a write sequence (after /CAL and /WE
EDRAM Basic Operating Modes
Function
Read Hit
Read Miss
Write Hit
Write Miss
Internal Refresh
Low Power Standby
Unallowed Mode
Low Power Self
Refresh Option
/S
L
L
L
L
X
H
H
H
/RE
↓
↓
↓
↓
↓
H
L
↓
W/R
L
L
H
H
X
X
X
X
/F
H
H
H
H
L
X
H
H
/CAL
H
H
H
H
X
H
X
L
/WE
X
X
H
H
X
H
X
H
A
0-10
Row = LRR
Row
≠
LRR
Row = LRR
Row
≠
LRR
X
X
X
X
Comment
No DRAM Reference, Data in Cache
DRAM Row to Cache
Write to DRAM and Cache, Reads Enabled
Write to DRAM, Cache Not Updated, Reads Disabled
Cache Reads Enabled
Standby Current
Unallowed Mode (Except -L Option)
Standby Current, Internal Refresh Clock
H = High; L = Low; X = Don’t Care;
↓
= High-to-Low Transition; LRR = Last Row Read
2-97
are brought high and t
RE
is satisfied), /RE can be brought high to
precharge the memory. It is possible to perform cache reads
concurrently with the precharge. During write sequences, a write
operation is not performed unless both /CAL and /WE are low. As a
result, /CAL can be used as a byte write select in multi-chip systems. If
/CAL is not clocked on a write sequence, the memory will perform a
/RE only refresh to the selected row and data will remain unmodified.
refresh period. A
10
does not need to be cycled. Read refresh cycles
are not allowed because a DRAM refresh cycle does not occur when a
read refresh address matches the LRR address latch.
/RE Inactive Operation
It is possible to read data from the SRAM cache without clocking
/RE. This option is desirable when the external control logic is capable
of fast hit/miss comparison. In this case, the controller can avoid the
time required to perform row/column multiplexing on hit cycles. This
capability also allows the EDRAM to perform cache read operations
during precharge and refresh cycles to minimize wait states. It is only
necessary to select /S for the selected bank (/S
0
or /S
1
) and /G and
provide the appropriate column address to read data. The row address
of the SRAM cache accessed without clocking /RE will be specified by
the LRR address latch loaded during the last /RE active read cycle. To
perform a cache read, /CAL is clocked to latch the column address.
The cache data is valid at time t
CLV
after the column address is setup to
/CAL.
Write-Per-Bit Operation
The DM2M36SJ EDRAM SIMM provides a write-per-bit capability
to selectively modify individual parity bits (DQ
8,17,26,35
) for byte write
operations. The parity devices (DM2252) are selected via /CAL
P
. Data
bits do not require or support write-per-bit capability. Byte write
selection to non-parity bits is accomplished via /CAL
0-3
. The bits to be
written are determined by a bit mask data word which is placed on
the parity I/O data pins prior to clocking /RE. The logic one bits in the
mask data select the bits to be written. As soon as the mask is latched
by /RE, the mask data is removed and write data can be placed on the
databus. The mask is only specified on the /RE transition. During page
mode burst write operations, the same mask is used for all write
operations.
Internal Refresh
If /F is active (low) on the assertion of /RE, an internal refresh
cycle is executed. This cycle refreshes the row address supplied by an
internal refresh counter. This counter is incremented at the end of the
cycle in preparation for the next /F refresh cycle. At least 1,024 /F
cycles must be executed every 64ms. /F refresh cycles can be hidden
because cache memory can be read under column address control
throughout the entire /F cycle. /F cycles are the only active cycles
during which /S can be disabled.
/CAL Before /RE Refresh (“/CAS Before /RAS”)
/CAL before /RE refresh, a special case of internal refresh, is
discussed in the “Reduced Pin Count Operation” section below.
/RE Only Refresh Operation
Although /F refresh using the internal refresh counter is the
recommended method of EDRAM refresh, it is possible to perform an
/RE only refresh using an externally supplied row address. /RE refresh
is performed by executing a
write cycle
(W/R and /F are high) where
/CAL is not clocked. This is necessary so that the current cache
contents and LRR are not modified by the refresh operation. All
combinations of addresses A
0-9
must be sequenced every 64ms
+3.3 Volt Power Supply Operation
If the +3.3 volt power supply option is specified, the EDRAM will
operate from a +3.3 volt +0.3 volt power supply and all inputs and
outputs will have LVTTL/LVCMOS compatible signal levels. The +3.3
volt EDRAM will not accept input levels which exceed the power
supply voltage. If mixed I/O levels are expected in your system, please
specify the +5 volt version of the EDRAM.
Low Power Mode
The EDRAM enters its low power mode when /S is high. In this
mode, the internal DRAM circuitry is powered down to reduce
standby current.
Low Power, Self-Refresh Option
When the low power, self refresh mode option is specified when
ordering the EDRAM, the EDRAM enters this mode when /RE is
clocked while /S, W/R, /F, and /WE are high; and /CAL is low. In this
mode, the power is turned off to all I/O pins except /RE to minimize
chip power, and an on-board refresh clock is enabled to perform self-
refresh cycles using the on-board refresh counter. The EDRAM
remains in this low power mode until /RE is brought high again to
terminate the mode. The EDRAM /RE input must remain high for t
RP2
following exit from self-refresh mode to allow any on-going internal
refresh to terminate prior to the next memory operation.
Initialization Cycles
A minimum of eight /RE active initialization cycle (read, write or
refresh) are required before normal operations is guaranteed.
Following these start-up cycles, two read cycles to different row
addresses must be performed for each of the four internal banks of
DRAM to initialize the internal cache logic. Row address bits A
2
and
A
9
define the four internal DRAM banks. /RE must be high for 300ns
prior to initialization.
Unallowed Mode
Read, write, or /RE only operations must not be initiated to
unselected memory banks by clocking /RE when /S is high.
Reduced Pin Count Operation
It is possible to simplify the interface to the 8Mbyte SIMM to
reduce the number of control lines. /RE0 and /RE2 could be tied
together externally to provide a single row enable for bank 0. W/R
and /G can be tied together if reads are not performed during write
hit cycles. This external wiring simplifies the interface without any
performance impact.
Pin Descriptions
/RE
0,2,3
— Row Enable
This input is used to initiate DRAM read and write operations
and latch a row address as well as the states of W/R and /F. It is not
necessary to clock /RE to read data from the EDRAM SRAM row
registers. On read operations, /RE can be brought high as soon as
data is loaded into cache to allow early precharge. /RE to bank 0
and bank 1 must be clocked separately and only clocked during
DRAM operations to the selected bank.
2-98
Pinout
Interconnect
Pin No. Function (Component Pin)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
GND
DQ
0
DQ
18
DQ
1
DQ
19
DQ
2
DQ
20
DQ
3
DQ
21
C (8,21,28)
U1,10 (27)
U2,11 (24)
U1,10 (26)
U2,11 (25)
U1,10 (25)
U2,11 (26)
U1,10 (24)
U2,11 (27)
Ground
Byte 1 I/O 1
Byte 3 I/O 1
Byte 1 I/O 2
Byte 3 I/O 2
Byte 1 I/O 3
Byte 3 I/O 3
Byte 1 I/O 4
Byte 3 I/O 4
V
CC
V
CC
Address
Address
Address
Address
Address
Address
Address
Address
Byte 1 I/O 5
Byte 3 I/O 5
Byte 1 I/O 6
Byte 3 I/O 6
Byte 1 I/O 7
Byte 3 I/O 7
Byte 1 I/O 8
Byte 3 I/O 8
Address
Ground
V
CC
Address
Address
Bank 1 Row Enable
Bank 0 Row Enable (Bytes 3,4, Parity)
Parity I/O for Byte 3
Parity I/O for Byte 1
Organization
Interconnect
Pin No. Function (Component Pin)
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
DQ
17
*
DQ
35
*
GND
/CAL
0
/CAL
2
/CAL
3
/CAL
1
/RE
0
/S
1
/CAL
P
*
/WE
W/R
DQ
9
DQ
27
DQ
10
DQ
28
DQ
11
DQ
29
DQ
12
DQ
30
DQ
13
DQ
31
+5/3.3 V
DQ
32
DQ
14
DQ
33
DQ
15
DQ
34
DQ
16
+5/3.3 V
/G
/F
/S
0
PD
GND
GND
U5,14 (25)
U5,14 (24)
C (8,21,28)
U1,3,10,12 (16)
U2,4,11,13 (16)
U7,8,16,17 (16)
U6,9,15,18 (16)
U1,3,6,9 (6)
U10-18 (19)
U5,14 (16)
C (20)
C (17)
U6,15 (27)
U7,16 (27)
U6,15 (26)
U7,16 (26)
U6,15 (25)
U7,16 (25)
U6,15 (24)
U7,16 (24)
U9,18 (24)
U8,17 (24)
C (7,14,22)
U8,17 (26)
U9,18 (25)
U8,17 (25)
U9,18 (26)
U8,17 (24)
U9,18 (27)
C (7,14,22)
C (23)
C (18)
U1-9 (19)
Signal GND
C (8,21,28)
C (8,21,28)
Organization
Parity I/O for Byte 2
Parity I/O for Byte 4
Ground
Byte 1 Column Address Latch
Byte 3 Column Address Latch
Byte 4 Column Address Latch
Byte 2 Column Address Latch
Bank 0 Row Enable (Bytes 1,2)
Chip Select Bank 1
Parity Column Address Latch
Write Enable
W/R Mode Control
Byte 2 I/O 1
Byte 4 I/O 1
Byte 2 I/O 2
Byte 4 I/O 2
Byte 2 I/O 3
Byte 4 I/O 3
Byte 2 I/O 4
Byte 4 I/O 4
Byte 2 I/O 5
Byte 4 I/O 5
V
CC
Byte 4 I/O 6
Byte 2 I/O 6
Byte 4 I/O 7
Byte 2 I/O 7
Byte 4 I/O 8
Byte 2 I/O 8
V
CC
Output Enable
Refresh Mode Control
Chip Select Bank 0
Presence Detect
Ground
Ground
*No Connect for DM2M32SJ
+5/3.3 V C (7,14,22)
+5/3.3 V C (7,14,22)
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
10
DQ
4
DQ
22
DQ
5
DQ
23
DQ
6
DQ
24
DQ
7
DQ
25
A
7
GND
C (1)
C (2)
C (12)
C (3)
C (4)
C (5)
C (9)
C (15)
U3,12 (27)
U4,13 (24)
U3,12 (26)
U4,13 (25)
U3,12 (25)
U4,13 (26)
U3,12 (24)
U4,13 (27)
C (10)
C (8,21,28)
+5/3.3 V C (7,14,22)
A
8
A
9
/RE
3
/RE
2
DQ
26
*
DQ
8
*
C (11)
C (13)
U10-18 (6)
U2,4,5,7,8 (6)
U5,14 (27)
U5,14 (26)
C = Common to All Memory Chips, U1 = Chip 1, etc.
2-99
51mcu
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