FEATURES .................................................................................................................................................................. 4
GENERAL DESCRIPTION ......................................................................................................................................... 5
Figure 1. Serial Peripheral Interface Modes Supported ....................................................................................... 8
DATA PROTECTION.................................................................................................................................................... 9
Table 2. Protected Area Sizes .............................................................................................................................. 9
HOLD FEATURE........................................................................................................................................................ 10
Status Register Bits ........................................................................................................................................... 13
(4) Write Status Register (WRSR) ...................................................................................................................... 14
POWER-ON STATE ................................................................................................................................................... 25
ERASE AND PROGRAMMING PERFORMANCE .................................................................................................... 43
DATA RETENTION ................................................................................................................................................... 43
ORDERING INFORMATION ...................................................................................................................................... 44
PART NAME DESCRIPTION ..................................................................................................................................... 45
PACKAGE INFORMATION ........................................................................................................................................ 46
REVISION HISTORY ................................................................................................................................................. 48
P/N: PM1709
3
REV. 1.3, DEC. 09, 2013
MX25V2006E
2M-BIT [x 1/x 2] CMOS SERIAL FLASH
FEATURES
GENERAL
• Serial Peripheral Interface compatible -- Mode 0 and Mode 3
• 2,097,152 x 1 bit structure or 1,048,576 x 2 bits (Dual Output mode) structure
• 64 Equal Sectors with 4K byte each
- Any Sector can be erased individually
• 4 Equal Blocks with 64K byte each
- Any Block can be erased individually
• Single Power Supply Operation
- 2.35 to 3.6 volt for read, erase, and program operations
• Latch-up protected to 100mA from -1V to Vcc +1V
PERFORMANCE
• High Performance
- Fast access time: 75MHz serial clock
- Serial clock of Dual Output mode: 70MHz
- Fast program time: 0.6ms(typ.) and 1ms(max.)/page (256-byte per page)
- Byte program time: 9us (typ.)
- Fast erase time: 40ms(typ.)/sector (4K-byte per sector) ; 0.4s(typ.)/block (64K-byte per block)
• Low Power Consumption
- Low active read current: 12mA(max.) at 75MHz and 4mA(max.) at 33MHz
- Low active programming current: 15mA (typ.)
- Low active sector erase current: 9mA (typ.)
- Low standby current: 15uA (typ.)
- Deep power-down mode 2uA (typ.)
• Minimum 100,000 erase/program cycles
• 20 years data retention
SOFTWARE FEATURES
• Input Data Format
- 1-byte Command code
• Block Lock protection
- The BP0~BP1 status bit defines the size of the area to be software protected against Program and Erase in-
structions
• Auto Erase and Auto Program Algorithm
-
Automatically erases and verifies data at selected sector
-
Automatically programs and verifies data at selected page by an internal algorithm that automatically times the
program pulse widths (Any page to be programed should have page in the erased state first)
•
Status Register Feature
•
Electronic Identification
-
JEDEC 2-byte Device ID
- RES command, 1-byte Device ID
•
Support Serial Flash Discoverable Parameters (SFDP) mode
HARDWARE FEATURES
• PACKAGE
-
8-pin SOP (150mil)
- 8-land WSON (6x5mm, 0.8mm package height)
-
All devices are RoHS Compliant and Halogen-free
P/N: PM1709
4
REV. 1.3, DEC. 09, 2013
MX25V2006E
GENERAL DESCRIPTION
The device features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus.
The four bus signals are a clock input (SCLK), a serial data input (SI), a serial data output (SO), and a chip select (CS#).
Serial access to the device is enabled by CS# input.
When it is in Dual Output read mode, the SI and SO pins become SIO0 and SIO1 pins for data output.
The device provides sequential read operation on whole chip.
After program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci-
fied page or sector/block locations will be executed. Program command is executed on byte basis, or page basis, or
word basis for erase command is executes on sector, or block, or whole chip basis.
To provide user with ease of interface, a status register is included to indicate the status of the chip. The status read
command can be issued to detect completion status of a program or erase operation via WIP bit.
When the device is not in operation and CS# is high, it is put in standby mode.
The device utilizes Macronix's proprietary memory cell, which reliably stores memory contents even after 100,000
For details, please refer to the official website [url=http://www.ti.com.cn/tool/cn/tmdsdsk5416]http://www.ti.com.cn/tool/cn/tmdsdsk5416[/url] I have not used the development board much, except for on...
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