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TS80C52X2-EIBD

Description
Microcontroller, 8-Bit, MROM, CMOS, PQFP44, PLASTIC, LCC-44
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size386KB,56 Pages
ManufacturerAtmel (Microchip)
Download Datasheet Parametric View All

TS80C52X2-EIBD Overview

Microcontroller, 8-Bit, MROM, CMOS, PQFP44, PLASTIC, LCC-44

TS80C52X2-EIBD Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerAtmel (Microchip)
Parts packaging codeLCC
package instructionQCCJ,
Contacts44
Reach Compliance Codecompliant
Has ADCNO
Address bus width16
bit size8
DAC channelNO
DMA channelNO
External data bus width8
JESD-30 codeS-PQCC-J44
JESD-609 codee0
length16.6 mm
Humidity sensitivity level1
Number of I/O lines32
Number of terminals44
Maximum operating temperature85 °C
Minimum operating temperature-40 °C
PWM channelNO
Package body materialPLASTIC/EPOXY
encapsulated codeQCCJ
Package shapeSQUARE
Package formCHIP CARRIER
Peak Reflow Temperature (Celsius)225
Certification statusNot Qualified
ROM programmabilityMROM
Maximum seat height4.57 mm
surface mountYES
technologyCMOS
Temperature levelINDUSTRIAL
Terminal surfaceTIN LEAD
Terminal formJ BEND
Terminal pitch1.27 mm
Terminal locationQUAD
Maximum time at peak reflow temperature30
width16.6 mm
uPs/uCs/peripheral integrated circuit typeMICROCONTROLLER
TS80C32X2
TS87C52X2
TS80C52X2
8-bit Microcontroller 8 Kbytes ROM/OTP, ROMless
1. Description
TS80C52X2 is high performance CMOS ROM, OTP,
EPROM and ROMless versions of the 80C51 CMOS
single chip 8-bit microcontroller.
The TS80C52X2 retains all features of the 80C51 with
extended ROM/EPROM capacity (8 Kbytes), 256 bytes
of internal RAM, a 6-source , 4-level interrupt system,
an on-chip oscilator and three timer/counters.
In addition, the TS80C52X2 has a dual data pointer, a
more versatile serial channel that facilitates
multiprocessor communication (EUART) and a X2 speed
improvement mechanism.
The fully static design of the TS80C52X2 allows to
reduce system power consumption by bringing the clock
frequency down to any value, even DC, without loss of
data.
The TS80C52X2 has 2 software-selectable modes of
reduced activity for further reduction in power
consumption. In the idle mode the CPU is frozen while
the timers, the serial port and the interrupt system are still
operating. In the power-down mode the RAM is saved
and all other functions are inoperative.
2. Features
q
80C52 Compatible
8051 pin and instruction compatible
Four 8-bit I/O ports
Three 16-bit timer/counters
256 bytes scratchpad RAM
q
Interrupt Structure with
6 Interrupt sources,
4 level priority interrupt system
q
Full duplex Enhanced UART
Framing error detection
Automatic address recognition
q
High-Speed Architecture
40 MHz @ 5V, 30MHz @ 3V
X2 Speed Improvement capability (6 clocks/
machine cycle)
30 MHz @ 5V, 20 MHz @ 3V (Equivalent to
60 MHz @ 5V, 40 MHz @ 3V)
q
q
Low EMI (inhibit ALE)
Power Control modes
Idle mode
Power-down mode
Power-off Flag
q
q
q
Dual Data Pointer
On-chip ROM/EPROM (8Kbytes)
Programmable Clock Out and Up/Down Timer/
Counter 2
Asynchronous port reset
q
q
q
q
Once mode (On-chip Emulation)
Power supply: 4.5-5.5V, 2.7-5.5V
Temperature ranges: Commercial (0 to 70
o
C) and
Industrial (-40 to 85
o
C)
Packages: PDIL40, PLCC44, VQFP44 1.4, PQFP F1
(13.9 footprint), CQPJ44 (window), CDIL40
(window)
q
Rev.D - 16 November, 2000
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