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M366S6453AT0-C1H

Description
Synchronous DRAM Module, 64MX64, 6ns, CMOS, DIMM-168
Categorystorage    storage   
File Size149KB,9 Pages
ManufacturerSAMSUNG
Websitehttp://www.samsung.com/Products/Semiconductor/
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M366S6453AT0-C1H Overview

Synchronous DRAM Module, 64MX64, 6ns, CMOS, DIMM-168

M366S6453AT0-C1H Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerSAMSUNG
Parts packaging codeDIMM
package instructionDIMM, DIMM168
Contacts168
Reach Compliance Codecompliant
ECCN codeEAR99
access modeFOUR BANK PAGE BURST
Maximum access time6 ns
Other featuresAUTO/SELF REFRESH
Maximum clock frequency (fCLK)100 MHz
I/O typeCOMMON
JESD-30 codeR-XDMA-N168
memory density4294967296 bit
Memory IC TypeSYNCHRONOUS DRAM MODULE
memory width64
Humidity sensitivity level1
Number of functions1
Number of ports1
Number of terminals168
word count67108864 words
character code64000000
Operating modeSYNCHRONOUS
Maximum operating temperature70 °C
Minimum operating temperature
organize64MX64
Output characteristics3-STATE
Package body materialUNSPECIFIED
encapsulated codeDIMM
Encapsulate equivalent codeDIMM168
Package shapeRECTANGULAR
Package formMICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)225
power supply3.3 V
Certification statusNot Qualified
refresh cycle8192
self refreshYES
Maximum standby current0.032 A
Maximum slew rate1.84 mA
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountNO
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formNO LEAD
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperatureNOT SPECIFIED
M366S6453AT0
M366S6453AT0 SDRAM DIMM
PC100 Unbuffered DIMM
64Mx64 SDRAM DIMM based on 32Mx8, 4Banks, 8K Refresh, 3.3V Synchronous DRAMs with SPD
GENERAL DESCRIPTION
The Samsung M366S6453AT0 is a 64M bit x 64 Synchronous
Dynamic RAM high density memory module. The Samsung
M366S6453AT0 consists of sixteen CMOS 32M x 8 bit with
4banks Synchronous DRAMs in TSOP-II 400mil package and a
2K EEPROM in 8-pin TSSOP package on a 168-pin glass-epoxy
substrate. Two 0.1uF decoupling capacitors are mounted on the
printed circuit board in parallel for each SDRAM.
The M366S6453AT0 is a Dual In-line Memory Module and is
intended for mounting into 168-pin edge connector sockets.
Synchronous design allows precise cycle control with the use of
system clock. I/O transactions are possible on every clock cycle.
Range of operating frequencies, programmable latencies allows
the same device to be useful for a variety of high bandwidth, high
performance memory system applications.
FEATURE
• Performance range
Part No.
M366S6453AT0-C80
M366S6453AT0-C1H
M366S6453AT0-C1L
Max Freq. (Speed)
125MHz (8ns @ CL=3)
100MHz (10ns @ CL=2)
100MHz (10ns @ CL=3)
Burst mode operation
Auto & self refresh capability (8192 Cycles/64ms)
LVTTL compatible inputs and outputs
Single 3.3V
±
0.3V power supply
MRS cycle with address key programs
Latency (Access from column address)
Burst length (1, 2, 4, 8 & Full page)
Data scramble (Sequential & Interleave)
• All inputs are sampled at the positive going edge of the
system clock
• Serial presence detect with EEPROM
• PCB :
Height (1,375mil),
double sided component
PIN CONFIGURATIONS (Front side/back side)
Pin Front Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
V
SS
DQ0
DQ1
DQ2
DQ3
V
DD
DQ4
DQ5
DQ6
DQ7
DQ8
V
SS
DQ9
DQ10
DQ11
DQ12
DQ13
V
DD
DQ14
DQ15
*CB0
*CB1
V
SS
NC
NC
V
DD
WE
DQM0
Front
Pin Front Pin
DQ18
DQ19
V
DD
DQ20
NC
*V
REF
CKE1
V
SS
DQ21
DQ22
DQ23
V
SS
DQ24
DQ25
DQ26
DQ27
V
DD
DQ28
DQ29
DQ30
DQ31
V
SS
CLK2
NC
WP
**SDA
**SCL
V
DD
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
Back
V
SS
DQ32
DQ33
DQ34
DQ35
V
DD
DQ36
DQ37
DQ38
DQ39
DQ40
V
SS
DQ41
DQ42
DQ43
DQ44
DQ45
V
DD
DQ46
DQ47
*CB4
*CB5
V
SS
NC
NC
V
DD
CAS
DQM4
Pin
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
Back
DQM5
CS1
RAS
V
SS
A1
A3
A5
A7
A9
BA0
A11
V
DD
CLK1
A12
V
SS
CKE0
CS3
DQM6
DQM7
A13
V
DD
NC
NC
*CB6
*CB7
V
SS
DQ48
DQ49
Pin
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
Back
DQ50
DQ51
V
DD
DQ52
NC
*V
REF
NC
V
SS
DQ53
DQ54
DQ55
V
SS
DQ56
DQ57
DQ58
DQ59
V
DD
DQ60
DQ61
DQ62
DQ63
V
SS
CLK3
NC
**SA0
**SA1
**SA2
V
DD
29 DQM1 57
58
CS0
30
59
31
DU
60
32
V
SS
61
33
A0
62
34
A2
63
35
A4
64
36
A6
65
37
A8
38 A10/AP 66
67
39
BA1
68
40
V
DD
69
41
V
DD
42 CLK0 70
71
43
V
SS
72
44
DU
73
45
CS2
46 DQM2 74
47 DQM3 75
76
48
DU
77
49
V
DD
78
50
NC
79
51
NC
52 *CB2 80
53 *CB3 81
82
54
V
SS
55 DQ16 83
56 DQ17 84
PIN NAMES
Pin Name
A0 ~ A12
BA0 ~ BA1
DQ0 ~ DQ63
CLK0 ~ CLK3
CS0 ~ CS3
RAS
CAS
WE
DQM0 ~ 7
V
DD
V
SS
*V
REF
SDA
SCL
SA0 ~ 2
WP
DU
NC
Function
Address input (Multiplexed)
Select bank
Data input/output
Clock input
Chip select input
Row address strobe
Column address strobe
Write enable
DQM
Power supply (3.3V)
Ground
Power supply for reference
Serial data I/O
Serial clock
Address in EEPROM
Write protection
Don′t use
No connection
CKE0 ~ CKE1 Clock enable input
* These pins are not used in this module.
**
These pins should be NC in the system
which does not support SPD.
SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 0.0 Sep. 1999

M366S6453AT0-C1H Related Products

M366S6453AT0-C1H M366S6453AT0-C1L M366S6453AT0-C80
Description Synchronous DRAM Module, 64MX64, 6ns, CMOS, DIMM-168 Synchronous DRAM Module, 64MX64, 6ns, CMOS, DIMM-168 Synchronous DRAM Module, 64MX64, 6ns, CMOS, DIMM-168
Is it Rohs certified? incompatible incompatible incompatible
Parts packaging code DIMM DIMM DIMM
package instruction DIMM, DIMM168 DIMM, DIMM168 DIMM, DIMM168
Contacts 168 168 168
Reach Compliance Code compliant compliant compliant
ECCN code EAR99 EAR99 EAR99
access mode FOUR BANK PAGE BURST FOUR BANK PAGE BURST FOUR BANK PAGE BURST
Maximum access time 6 ns 6 ns 6 ns
Other features AUTO/SELF REFRESH AUTO/SELF REFRESH AUTO/SELF REFRESH
Maximum clock frequency (fCLK) 100 MHz 100 MHz 125 MHz
I/O type COMMON COMMON COMMON
JESD-30 code R-XDMA-N168 R-XDMA-N168 R-XDMA-N168
memory density 4294967296 bit 4294967296 bit 4294967296 bit
Memory IC Type SYNCHRONOUS DRAM MODULE SYNCHRONOUS DRAM MODULE SYNCHRONOUS DRAM MODULE
memory width 64 64 64
Humidity sensitivity level 1 1 1
Number of functions 1 1 1
Number of ports 1 1 1
Number of terminals 168 168 168
word count 67108864 words 67108864 words 67108864 words
character code 64000000 64000000 64000000
Operating mode SYNCHRONOUS SYNCHRONOUS SYNCHRONOUS
Maximum operating temperature 70 °C 70 °C 70 °C
organize 64MX64 64MX64 64MX64
Output characteristics 3-STATE 3-STATE 3-STATE
Package body material UNSPECIFIED UNSPECIFIED UNSPECIFIED
encapsulated code DIMM DIMM DIMM
Encapsulate equivalent code DIMM168 DIMM168 DIMM168
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form MICROELECTRONIC ASSEMBLY MICROELECTRONIC ASSEMBLY MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius) 225 225 225
power supply 3.3 V 3.3 V 3.3 V
Certification status Not Qualified Not Qualified Not Qualified
refresh cycle 8192 8192 8192
self refresh YES YES YES
Maximum standby current 0.032 A 0.032 A 0.032 A
Maximum slew rate 1.84 mA 1.84 mA 1.92 mA
Maximum supply voltage (Vsup) 3.6 V 3.6 V 3.6 V
Minimum supply voltage (Vsup) 3 V 3 V 3 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V
surface mount NO NO NO
technology CMOS CMOS CMOS
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL
Terminal form NO LEAD NO LEAD NO LEAD
Terminal pitch 1.27 mm 1.27 mm 1.27 mm
Terminal location DUAL DUAL DUAL
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED NOT SPECIFIED
Maker SAMSUNG - SAMSUNG
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