EDI88512CA
512Kx8 Monolithic SRAM, SMD 5962-95600
FEATURES
■
Access Times of 15, 17, 20, 25, 35, 45, 55ns
■
Data Retention Function (LPA version)
■
TTL Compatible Inputs and Outputs
■
Fully Static, No Clocks
■
Organized as 512Kx8
■
Commercial, Industrial and Military Temperature Ranges
■
32 lead JEDEC Approved Evolutionary Pinout
• Ceramic Sidebrazed 600 mil DIP (Package 9)
• Ceramic Sidebrazed 400 mil DIP (Package 326)
• Ceramic 32 pin Flatpack (Package 344)
• Ceramic Thin Flatpack (Package 321)
• Ceramic SOJ (Package 140)
■
36 lead JEDEC Approved Revolutionary Pinout
• Ceramic Flatpack (Package 316)
• Ceramic SOJ (Package 327)
• Ceramic LCC (Package 502)
■
Single +5V (±10%) Supply Operation
The EDI88512CA is a 4 megabit Monolithic CMOS
Static RAM.
The 32 pin DIP pinout adheres to the JEDEC evolu-
tionary standard for the four megabit device. All 32 pin
packages are pin for pin upgrades for the single chip
enable 128K x 8, the EDI88128CS. Pins 1 and 30 be-
come the higher order addresses.
The 36 pin revolutionary pinout also adheres to the
JEDEC standard for the four megabit device. The cen-
ter pin power and ground pins help to reduce noise in
high performance systems. The 36 pin pinout also
allows the user an upgrade path to the future 2Mx8.
A Low Power version with Data Retention
(EDI88512LPA) is also available for battery backed
applications. Military product is available compliant to
Appendix A of MIL-PRF-38535.
FIG. 1
PIN CONFIGURATION
36 P
IN
T
OP
V
IEW
A18
A16
A14
A12
A7
A6
A5
A4
A3
A2
A1
A0
I/O0
I/O1
I/O2
V
SS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
P
IN
D
ESCRIPTION
32 P
IN
T
OP
V
IEW
32 V
CC
31 A15
30 A17
29 WE
28 A13
27 A8
26 A9
25 A11
24 OE
23 A10
22 CS
21 I/O7
20 I/O6
19 I/O5
18 I/O4
17 I/O3
A
-18
I/O
0-7
Data Inputs/Outputs
A
0-18
WE
CS
OE
V
CC
V
SS
NC
Address Inputs
Write Enables
Chip Selects
Output Enable
Power (+5V ±10%)
Ground
Not Connected
B
LOCK
D
IAGRAM
Memory Array
Address
Buffer
Address
Decoder
I/O
Circuits
I/O
-7
WE
CS
OE
Aug. 2002 Rev. 9
1
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI88512CA
A
BSOLUTE
M
AXIMUM
R
ATINGS
Parameter
Voltage on any pin relative to Vss
Operating Temperature T
A
(Ambient)
Commercial
Industrial
Military
Storage Temperature, Plastic
Power Dissipation
Output Current
Junction Temperature, T
J
-0.5 to 7.0
0 to +70
-40 to +85
-55 to +125
-65 to +150
1.5
20
175
Unit
V
°C
°C
°C
°C
W
mA
°C
OE
X
H
L
X
CS
H
L
L
L
WE
X
H
H
L
T
RUTH
T
ABLE
Mode
Output
Standby
High Z
Output Deselect High Z
Read
Data Out
Write
Data In
Power
Icc
2
, Icc
3
Icc
1
Icc
1
Icc
1
R
ECOMMENDED
O
PERATING
C
ONDITIONS
Parameter
Symbol
Supply Voltage
V
CC
Supply Voltage
V
SS
Input High Voltage
V
IH
Input Low Voltage
V
IL
Min
4.5
0
2.2
-0.3
Typ
5.0
0
—
—
Max
5.5
0
3.0
+0.8
Unit
V
V
V
V
NOTE:
Stress greater than those listed under "Absolute Maximum Ratings"
may cause permanent damage to the device. This is a stress rating
only and functional operation of the device at these or any other
conditions greater than those indicated in the operational sections of
this specification is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect reliability.
C
APACITANCE
(T
A
= +25°C)
Parameter
Symbol
Condition
Max Unit
Address Lines
C
I
V
IN
= Vcc or Vss, f = 1.0MHz 12 pF
Data Lines
C
O
V
OUT
= Vcc or Vss, f = 1.0MHz 14 pF
These parameters are sampled, not 100% tested.
DC C
HARACTERISTICS
(V
CC
= 5V, T
A
= -55°C
TO
+125°C)
Parameter
Input Leakage Current
Output Leakage Current
Operating Power Supply Current
Standby (TTL) Power Supply Current
Full Standby Power Supply Current
Output Low Voltage
Output High Voltage
Symbol
I
LI
I
LO
I
CC
1
I
CC
2
I
CC
3
V
OL
V
OH
Conditions
V
IN
= 0V to V
CC
V
I/O
= 0V to V
CC
WE, CS = V
IL
, I
I/O
= 0mA, Min Cycle
CS
³
V
IH
, V
IN
£
V
IL
, V
IN
³
V
IH
CS
³
V
CC
-0.2V
V
IN
³
Vcc -0.2V or V
IN
£
0.2V
I
OL
= 8.0mA
I
OH
= -4.0mA
Min
-10
-10
—
—
—
—
—
—
2.4
Max
10
10
250
225
60
25
20
0.4
—
Units
µA
µA
mA
mA
mA
mA
mA
V
V
(17ns)
(20 -55ns)
CA
LPA
NOTE: DC test conditions: V
IL
= 0.3V, V
IH
= Vcc -0.3V
AC TEST CONDITIONS
Figure 1
Vcc
Figure 2
Vcc
Input Pulse Levels
Input Rise and Fall Times
Input and Output Timing Levels
Output Load
480Ω
V
SS
to 3.0V
5ns
1.5V
Figure 1
480Ω
NOTE: For t
EHQZ
, t
GHQZ
and t
WLQZ
, CL = 5pF Figure 2)
Q
255Ω
30pF
Q
255Ω
5pF
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
2
EDI88512CA
AC C
HARACTERISTICS
– READ CYCLE
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C
TO
+125°C)
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Chip Enable to Output in Low Z (1)
Chip Disable to Output in High Z (1)
Output Hold from Address Change
Output Enable to Output Valid
Output Enable to Output in Low Z (1)
Output Disable to Output in High Z(1)
Symbol
JEDEC Alt.
t
AVAV
t
RC
t
AVQV
t
AA
t
ELQV
t
ACS
t
ELQX
t
CLZ
t
EHQZ
t
CHZ
t
AVQX
t
OH
t
GLQV
t
OE
t
GLQX
t
OLZ
t
GHQZ
t
OHZ
15ns
Min Max
15
15
15
2
0
7
0
8
0
0
7
17ns
Min Max
17
17
17
3
0
7
0
8
0
0
7
20ns
Min Max
20
20
20
3
0
8
0
10
0
0
8
25ns
35ns
45ns
55ns
Min Max Min Max Min Max Min Max Units
25
35
45
55
ns
25
35
45
55
ns
25
35
45
55
ns
3
3
3
3
ns
0 10
0 15
0 20
0 20
ns
0
0
0
0
ns
12
15
25
30
ns
0
0
0
0
ns
0 10
0 15
0 20
0 20
ns
1. This parameter is guaranteed by design but not tested.
AC C
HARACTERISTICS
– WRITE CYCLE
(V
CC
= 5.0V, V
SS
= 0V, T
A
= -55°C
TO
+125°C)
Parameter
Write Cycle Time
Chip Enable to End of Write
Address Setup Time
Address Valid to End of Write
Write Pulse Width
Write Recovery Time
Data Hold Time
Write to Output in High Z (1)
Data to Write Time
Output Active from End of Write (1)
Symbol
JEDEC Alt.
t
AVAV
t
W C
t
ELWH
t
C W
t
ELEH
t
C W
t
AVWL
t
AS
t
AVEL
t
AS
t
AVWH
t
AW
t
AVEH
t
AW
t
W LWH
t
W P
t
WLEH
t
W P
t
WHAX
t
W R
t
EHAX
t
W R
t
W HD X
t
DH
t
EHDX
t
DH
t
WLQZ
t
WHZ
t
D VWH
t
D W
t
DVEH
t
D W
t
WHQX
t
WLZ
15ns
17ns
Min Max Min Max
15
17
13
14
13
14
0
0
0
0
13
14
13
14
13
14
13
14
0
0
0
0
0
0
0
0
0
8
0
8
8
8
8
8
0
0
20ns
25ns
35ns
45ns
Min Max Min Max Min Max Min Max
20
25
35
45
15
17
25
30
15
17
25
30
0
0
0
0
0
0
0
0
15
17
25
30
15
17
25
30
15
17
25
30
15
17
25
30
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
8
0 10
0 25
0
30
10
12
20
25
10
12
20
25
0
0
0
0
55ns
Min Max Units
55
ns
50
ns
50
ns
0
ns
0
ns
50
ns
50
ns
45
ns
45
ns
0
ns
0
ns
0
ns
0
ns
0
30
ns
40
ns
30
ns
0
ns
1. This parameter is guaranteed by design but not tested.
3
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
EDI88512CA
FIG. 2 TIMING WAVEFORM - READ CYCLE
t
AVAV
ADDRESS
t
AVQV
t
AVAV
ADDRESS
ADDRESS 1
ADDRESS 2
CS
t
ELQV
t
ELQX
OE
t
EHQZ
t
AVQV
DATA I/O
t
AVQX
DATA
1
DATA 2
t
GLQV
t
GLQX
DATA OUT
t
GHQZ
READ CYCLE 1 (WE HIGH; OE, CS LOW)
READ CYCLE 2 (WE HIGH)
FIG. 3 WRITE CYCLE - WE CONTROLLED
t
AVAV
ADDRESS
t
AVWH
t
ELWH
CS
t
WHAX
t
AVWL
WE
t
WLWH
t
DVWH
t
WHDX
DATA IN
DATA VALID
t
WLQZ
DATA OUT
HIGH Z
t
WHQX
WRITE CYCLE 1, WE CONTROLLED
FIG. 4 WRITE CYCLE - CS CONTROLLED
t
AVAV
ADDRESS
t
AVEH
t
ELEH
CS
WS32K32-XHX
t
EHAX
t
WLEH
t
DVEH
t
EHDX
t
AVEL
WE
DATA IN
DATA OUT
HIGH Z
DATA VALID
WRITE CYCLE 2, CS CONTROLLED
White Electronic Designs Corporation • Phoenix AZ • (602) 437-1520
4
EDI88512CA
D
ATA
R
ETENTION
C
HARACTERISTICS
(EDI88512LPA ONLY)
(T
A
= -55°C
TO
+125°C)
Characteristic
Low Power Version only
Data Retention Voltage
Data Retention Quiescent Current
Chip Disable to Data Retention Time
Operation Recovery Time
Sym
V
DD
I
CCDR
T
CDR
T
R
Conditions
V
DD
= 2.0V
CS
³
V
DD
-0.2V
V
IN
³
V
DD
-0.2V
or V
IN
£
0.2V
Min
2
–
0
T
AVAV
Typ
–
–
–
–
Max
–
2
–
–
Units
V
mA
ns
ns
FIG. 5 DATA RETENTION - CS CONTROLLED
DATA RETENTION MODE
V
CC
t
CDR
CS
CS = V
DD
-0.2V
4.5V
V
DD
WS32K32-XHX
4.5V
t
R
DATA RETENTION, CS CONTROLLED
5
White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com
FPGA/CPLD
京公网安备 11010802033920号
EEWORLD
