MAH3690CS datasheet, PDF - EEWORLD Datasheet

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MAH3690CS: DescriptionMil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CDIP48; CategoryThe embedded processor and controller Microcontrollers and processors; File Size425KB，41 Pages; ManufacturerDynex; Websitehttp://www.dynexsemi.com/

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MAH3690CS Overview

Mil-Std-1553 Controller, 2 Channel(s), 0.125MBps, CMOS, CDIP48

MAH3690CS Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Dynex
package instruction	DIP, DIP48,.6
Reach Compliance Code	unknown
Other features	DUAL BUS CAPABILITY; MA3690 & MA3691 IS A CHIP SET OF 1553B BUS CONTROLLER/REMOTE TERMINAL
Address bus width	2
boundary scan	NO
maximum clock frequency	12 MHz
letter of agreement	MIL-STD-1553B
Data encoding/decoding methods	BIPH-LEVEL(MANCHESTER)
Maximum data transfer rate	0.125 MBps
External data bus width	16
JESD-30 code	R-CDIP-T48
JESD-609 code	e0
low power mode	NO
Number of DMA channels
Number of I/O lines
Number of serial I/Os	2
Number of terminals	48
On-chip data RAM width
Maximum operating temperature	125 °C
Minimum operating temperature	-55 °C
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	DIP
Encapsulate equivalent code	DIP48,.6
Package shape	RECTANGULAR
Package form	IN-LINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
RAM (number of words)	0
Filter level	38535V;38534K;883S
Maximum slew rate	50 mA
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	NO
technology	CMOS
Temperature level	MILITARY
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	THROUGH-HOLE
Terminal pitch	2.54 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
uPs/uCs/peripheral integrated circuit type	SERIAL IO/COMMUNICATION CONTROLLER, MIL-STD-1553

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MA3690/1/3

1553B Bus Controller/Remote Terminal

Replaces June 1999 version, DS3587-4.0

DS3587-5.0 January 2000

The MA3690/1 chip set has three modes of operation:

remote terminal, bus controller, and passive monitor It has a

dual bus capability, requires minimum support hardware /

software and is implemented on a radiation hard, CMOS/SOS

process. For applications requiring access to Terminal Flag, a

48-Pin DIL MA3693 is available as an alternative to the

MA3690.

As a remote terminal, the MA3690/1 is fully compatible with

Mil-Std-1553B. The chip set obtained SEAFAC approval in

December 1987. All options and mode commands specified by

the Mil Std are implemented Full and meaningful use is made

of status word bits and a comprehensive bit word is provided.

A unique mechanism has been incorporated that allows

the subsystem to declare illegal commands legal, and vice

versa, before the chip set services the command. It should be

noted that use of this mechanism is optional and that the

system defaults to normal operation if the option is not

required. The chip set is easily interfaced to subsystem

memory and is sufficiently flexible to ensure compatibility with

a wide range of microprocessors.

As a bus controller the MA3690/1 has the ability to initiate

all types of 1553B transfer on either of the two buses An

instruction word is set up by the subsystem, prior to

transmission, which contains details of transfer type and bus

selection. Four bits of the instruction word have been used to

specify the conditions under which the chip set will generate a

subsystem interrupt. The most significant bits of the instruction

word have been used to specify the conditions under which the

chip set will perform an automatic retry and the number of

retries to be carried out (max. 3). At the end of each instruction

execution cycle, the chip set writes a report word into the

subsystem memory; the contents of which give the subsystem

an indication of the degree of success of the transfer.

The bus controller may be used in either of two

configurations, i.e. single shot or table driven.

In the single shot configuration, the controller is under

direct control from the subsystem (processor). In table driven

configuration, the controller is given greater autonomy to

execute a table of instructions held in either ROM or RAM.

As a passive monitor, the chip set will monitor all bus

activity and pass any associated information to the subsystem.

As the name implies, in this mode of operation, the chip set is

truly passive and will not reply to command instructions.

FEATURES

Radiation Hard to 1MRads (Si)

High SEU Immunity, Latch-Up Free

CMOS-SOS Technology

All Inputs and Outputs Fully TTL or CMOS Compatible

Military Temperature Range -55 to +125°C

Dual Bus Capability

Minimal Subsystem Interface

Powerful Bus Control Facility

Complete Remote Terminal Protocol

SEAFAC Approved

SIGNAL DESCRIPTIONS

All signals are TTL compatible unless stated otherwise. An

‘N’ at the end of the signal name denotes an active low signal.

SUPPLIES

VDD

VSS

5 volts positive supply

Ground

CLOCK INPUTS

CK12

12MHz clock

BUS INTERFACE LINES

PDIN0

Input

Positive threshold exceeded on bus 0.

NDIN0

Input

Negative threshold exceeded on bus 0.

TXEN0N

Output

Transmit enable for driver on bus 0.

PDOUT0N

Output

Positive Manchester data for driver on bus 0.

1/41

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