VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7961
Features
3.125Gb/s PECL Limiting Amplifier with LOS Detect
Applications
• SONET/SDH at 622Mb/s, 1.244Gb/s, 2.488Gb/s,
and 3.125Gb/s
• Full-Speed Fibre Channel (1.062Gb/s)
• Small Form Factor (SFF) Receivers
• ATM Optical Receivers
• 3.3V or 5V Power Supply
• Typical Supply Current of 32mA
• Positive Emitter-Coupled Logic (PECL) Outputs
• Optional Output Squelch
• Loss of Signal Detect
• Output Offset Correction
• Rise/Fall Times Faster than 100ps
• Packages: TSSOP-16, Bare Die
General Description
The VSC7961 is a single-supply limiting amplifier with Loss of Signal (LOS) detect for SONET/SDH and
Fibre Channel applications up to 3.125Gb/s. The VSC7961 provides a constant output signal swing for a wide
range of input voltages and has Positive Emitter-Coupled Logic (PECL). The VSC7959 provides the same func-
tionality as the VSC7961 with Current-Mode Logic (CML) outputs. Key features of the VSC7961 are its RMS
power detectors for programmable LOS detection, optional output squelch, adjustable output levels, excellent
jitter performance, and fast edge rates. The VSC7961 is available in die form or in a TSSOP-16 package.
Block Diagram
VSC7961
V
CC
8k
Ω
LOS
V
CC
8k
Ω
TH
RMS Power
Detect and
Control
IN+
LOS
SQUELCH
Output Control
LEVEL
OUT+
100Ω
IN-
OUT-
Lowpass Filter
10pF
CZ1
CZ2
Offset Correction
G52360-0, Rev 2.0
02/09/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 1
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
VSC7961
Electrical Characteristics
Table 1: DC Specifications
Symbol
V
CC
I
CC
I
EE
I
CCSQ
I
EESQ
I
SQ
PSSR
Parameter
Power Supply Voltage
Power Supply Current
(1)
Power Supply Current
(1)
Power Supply Current when
Squelched
(1)
Power Supply Current when
Squelched
(1)
Squelch Input Current
Power Supply Rejection Ratio
Min
3.135
Typ
59
62
31
35
58
62
20
23
Max
5.5
Units
V
mA
mA
mA
mΑ
mA
mA
mA
mA
Conditions
V
CC
= 3.3V
V
CC
= 5V
V
CC
= 3.3V
V
CC
= 5V
V
CC
= 3.3V
V
CC
= 5V
V
CC
= 3.3V
V
CC
= 5V
f < 2MHz
0
20
400
µA
dB
NOTE: (1) See Figure 4 for supply current measurement setup.
Table 2: DC Specifications
Symbol
V
IN
J
D
J
R
t
R,
t
F
V
N
R
DIFF
f
L
V
SQ
V
OH
V
OL
Z
O
Parameter
Data Rate
Input Voltage Range
Deterministic Jitter
Random Jitter
Rise and Fall Times
Input Referred Noise
Differential Input Resistance
Low Frequency Cutoff
Output Signal When Squelched
PECL Output High Voltage
PECL Output Low Voltage
Output Resistance
Min
3.125
10
Typ
Max
1200
25
8
100
230
Units
Gb/s
mV
ps
ps
ps
µV
Ω
MHz
kHz
mV
mV
mV
mV
mV
Ω
Conditions
Peak-to-peak
See Note 1
See Note 2, RMS
20% to 80%
RMS, IN+ to IN-
IN+ to IN-
C
Z
open
C
Z
= 0.1µF
Output AC-coupled
Squelched
Squelched
Single-ended
55
100
2
2
-1025
-1810
100
20
-850
-850
-1620
-1620
NOTES: (1) Deterministic jitter measured peak-to-peak with K28.5 pattern. (2) Random jitter measured with minimum input.
Page 2
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52360-0, Rev 2.0
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7961
Table 3: Loss of Signal Specifications
Symbol
H
LOS
I
LOS
V
THA
3.125Gb/s PECL Limiting Amplifier with LOS Detect
Parameter
LOS Hystersis
LOS Assert/Deassert Time
LOS Assert Threshold
Min
3.1
0.22
12.8
Typ
3.3
0.25
8.2
19.8
57.2
11.4
Max
5.5
0.28
21.8
Units
dB
µs
mV
mV
mV
mV
Conditions
H
LOS
= 20 log (V
THD
/V
THA
)
R
TH
= 2.5kΩ
R
TH
= 7kΩ
R
TH
= 20kΩ
R
TH
= 2.5kΩ
R
TH
= 7kΩ
R
TH
= 20kΩ
I
LOS
= –30µA
I
LOS
= +1.2µA
V
THD
V
LOSH
V
LOSL
LOS Deassert Threshold
LOS Output HIGH Voltage
LOS Output LOW Voltage
26.2
3.3
29.0
75.2
0.168
31.6
mV
mV
V
V
Table 4: Loss of Signal Truth Table
SQUELCH
High
Low
High
Low
LOS
Low
High
Low
Low
Output
Off
On
On
On
Absolute Maximum Ratings
(1)
Power Supply Voltage (V
CC
)............................................................................................................. -0.5V to +6V
Maximum Junction Temperature Range .........................................................................................................TBD
Storage Temperature Range (T
S
)................................................................................................. -55°C to +150°C
NOTE: (1) CAUTION: Stresses listed under “Absolute Maximum Ratings” may be applied to devices one at a time without caus-
ing permanent damage. Functionality at or above the values listed is not implied. Exposure to these values for extended
periods may affect device reliability.
Recommended Operating Conditions
Positive Voltage Rail (V
CC
).................................................................................................................. 3.3V or 5V
Junction Temperature Range (T
J
)................................................................................................ -40°C to +100°C
Ambient Temperature Range (T
A
)................................................................................................. -40°C to +85°C
G52360-0, Rev 2.0
02/09/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 3
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
3.125Gb/s PECL Limiting Amplifier with LOS Detect
VSC7961
Package Pin Descriptions
Figure 1: Pin Diagram
Top View
TSSOP-16 Package
CZ1
CZ2
GND
IN+
IN-
GND
NC
TH
1
2
3
4
5
6
7
8
16
15
14
13
NC
SQUELCH
VCC
OUT+
OUT-
VCC
LOS
LOS
VSC7961
12
11
10
9
Table 5: Pin Identifications
Pin Name
CZ1
CZ2
GND
IN+
IN-
GND
NC
TH
LOS
LOS
VCC
OUT-
OUT+
VCC
SQUELCH
NC
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
Offset Correction Loop Capacitor. Place capacitor between this pin and CZ2 to alter time constant
of offset correction loop. See
Detailed Description
section.
Offset Correction Loop Capacitor. Place capacitor between this pin and CZ1 to alter time constant
of offset correction loop. See
Detailed Description
section.
Supply Ground
Noninverted Input Signal
Inverted Input Signal
Supply Ground
This pin may be either connected to ground of left unconnected. This pin does not effet the
performance of the device.
Loss of Signal (LOS) Threshold. Connect a resistor from this pin to ground to set the input signal
level at which LOS outputs will be asserted. See
Application Information
section.
Inverted Loss of Signal Output. LOS is HIGH for input signals above the threshold programmed by
TH. See
Detailed Description
section.
Noninverted Loss of Signal Output. LOS is LOW for input signals above the threshold
programmed by TH. See
Detailed Description
section.
Power Supply
Inverted Data Output
Noninverted Data Output
Power Supply
Squelch Input. Squelch is disabled if this pin is unconnected or set LOW. When SQUELCH is
HIGH, OUT+ and OUT- are forced to static levels. See
Detailed Description
section.
No Connection
Page 4
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
G52360-0, Rev 2.0
02/09/01
VITESSE
SEMICONDUCTOR CORPORATION
Advance Product Information
VSC7961
Bare Die Descriptions
3.125Gb/s PECL Limiting Amplifier with LOS Detect
Figure 2: Pad Assignments
1597µm (0.06287")
Pad1
CAZ1
Pad 2
CAZ2
Pad 3
GNDA
Pad 4
LAINP
Pad 16
NC
Pad 15
SQ
Pad 14
VCCA
Pad 13
LAOP
1597µm
(0.06287")
VSC7961
Pad 5
LAINM
Pad 6
GNDA
Pad 7
NC
Pad 8
TH
Pad 9
LOS
Pad 12
LAOM
Pad 11
VCCA
Pad 10
LOS
Die Size:
Pad Pitch:
Pad Passivation Opening:
1597µm x 1597µm (0.06287" x 0.06287")
180µm (0.00709")
95µm x 95µm (0.00374" x 0.00374")
The back side of the die may either be left floating or connected ot ground.
G52360-0, Rev 2.0
02/09/01
©
VITESSE
SEMICONDUCTOR CORPORATION
• 741 Calle Plano • Camarillo, CA 93012
Tel: (800) VITESSE • FAX: (805) 987-5896 • Email: prodinfo@vitesse.com
Internet: www.vitesse.com
Page 5
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