W987Z6CBN80 datasheet, PDF - EEWORLD Datasheet

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W987Z6CBN80: DescriptionSynchronous DRAM, 8MX16, 6ns, CMOS, PBGA54, 8 X 9 MM, 1.20 MM HEIGHT, FBGA-54; Categorystorage storage; File Size2MB，46 Pages; ManufacturerWinbond Electronics Corporation; Websitehttp://www.winbond.com.tw

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W987Z6CBN80 Overview

Synchronous DRAM, 8MX16, 6ns, CMOS, PBGA54, 8 X 9 MM, 1.20 MM HEIGHT, FBGA-54

W987Z6CBN80 Parametric

Parameter Name	Attribute value
Maker	Winbond Electronics Corporation
Parts packaging code	BGA
package instruction	TFBGA,
Contacts	54
Reach Compliance Code	compliant
ECCN code	EAR99
access mode	FOUR BANK PAGE BURST
Maximum access time	6 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B54
JESD-609 code	e1
length	9 mm
memory density	134217728 bit
Memory IC Type	SYNCHRONOUS DRAM
memory width	16
Number of functions	1
Number of ports	1
Number of terminals	54
word count	8388608 words
character code	8000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	8MX16
Package body material	PLASTIC/EPOXY
encapsulated code	TFBGA
Package shape	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH
Certification status	Not Qualified
Maximum seat height	1.2 mm
self refresh	YES
Maximum supply voltage (Vsup)	3.6 V
Minimum supply voltage (Vsup)	2.7 V
Nominal supply voltage (Vsup)	3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	0.8 mm
Terminal location	BOTTOM
width	8 mm

W987Z6CBN80 Preview

Preliminary W987Z6CB

4 BANKS

16 BIT SDRAM

Table of Contents-

1. GENERAL DESCRIPTION ..................................................................................................................3

2. FEATURES ..........................................................................................................................................3

3. AVAILABLE PART NUMBER ..............................................................................................................3

4. BALL CONFIGURATION .....................................................................................................................4

5. BALL DESCRIPTION...........................................................................................................................5

6. BLOCK DIAGRAM ...............................................................................................................................6

7. ABSOLUTE MAXIMUM RATINGS ......................................................................................................7

8. DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS.......................................7

9. CAPACITANCE ...................................................................................................................................7

10. OPERATING CURRENT ...................................................................................................................8

11. AC CHARACTERISTICS AND OPERATING CONDITION...............................................................9

12. FUNCTIONAL DESCRIPTION ........................................................................................................12

Power Up Sequence.......................................................................................................................12

Command Function ........................................................................................................................12

Read Operation ..............................................................................................................................15

Write Operation...............................................................................................................................15

Precharge .......................................................................................................................................15

Burst Termination ...........................................................................................................................15

Interruption......................................................................................................................................16

Refresh Operation ..........................................................................................................................16

Power Down Mode .........................................................................................................................17

Mode Register Set Operation .........................................................................................................17

Simplified State Diagram ................................................................................................................19

13. TIMING WAVEFORMS....................................................................................................................20

Command Input Timing ..................................................................................................................20

Read Timing ...................................................................................................................................21

Control Timing of Input/Output Data...............................................................................................22

14. OPERATING TIMING EXAMPLE ....................................................................................................24

Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)........................................................24

Interleaved Bank Read (Burst Length = 4, CAS Latency = 3, Auto Precharge).............................25

Interleaved Bank Read (Burst Length = 8, CAS Latency = 3)........................................................26

Interleaved Bank Read (Burst Length = 8, CAS Latency = 3, Auto Precharge).............................27

-1-

Publication Release Date: June 24, 2002

Revision A1

Preliminary W987Z6CB

Interleaved Bank Write (Burst Length = 8) .....................................................................................28

Interleaved Bank Write (Burst Length = 8, Auto Precharge) ..........................................................29

Page Mode Read (Burst Length = 4, CAS Latency = 3) ................................................................30

Page Mode Read/Write (Burst Length = 8, CAS Latency = 3) .......................................................31

Auto Precharge Read (Burst Length = 4, CAS Latency = 3)..........................................................32

Auto Precharge Write (Burst Length = 4) .......................................................................................33

Auto Refresh Cycle.........................................................................................................................34

Self Refresh Cycle ..........................................................................................................................35

Burst Read and Single Write (Burst Length = 4, CAS Latency = 3)...............................................36

Power Down Mode .........................................................................................................................37

Auto Precharge Timing (Read Cycle).............................................................................................38

Auto Precharge Timing (Write Cycle) .............................................................................................39

Timing Chart of Read to Write Cycle ..............................................................................................40

Timing Chart of Write to Read Cycle ..............................................................................................40

Timing Chart of Burst Stop Cycle (Burst Stop Command) .............................................................41

Timing Chart of Burst Stop Cycle (Precharge Command) .............................................................41

CKE/DQM Input Timing (Write Cycle) ............................................................................................42

CKE/DQM Input Timing (Read Cycle) ............................................................................................43

Self Refresh / Power Down Mode Exit Timing................................................................................44

15. PACKAGE DIMENSION ..................................................................................................................45

16. REVISION HISTORY.......................................................................................................................46

-2-

Preliminary W987Z6CB

1. GENERAL DESCRIPTION

W987Z6CB is a high-speed synchronous dynamic random access memory (SDRAM), organized as

2M words

4 banks

16 bits. Using pipelined architecture and 0.175

µm

process technology,

W987Z6CB delivers a data bandwidth of up to 125M words per second (-8). For different application,

W987Z6CB is sorted into two speed grades: -75 and -8. The -75 is compliant to the 133 MHz/CL3

specification; the -8 is compliant to the 125 MHz/CL3 specification. For handheld device application,

these parts are specially designed with several power saving mechanisms to achieve extremely low

Self Refresh Current.

Accesses to the SDRAM are burst oriented. Consecutive memory location in one page can be

accessed at a burst length of 1, 2, 4, 8 or full page when a bank and row is selected by an ACTIVE

command. Column addresses are automatically generated by the SDRAM internal counter in burst

operation. Random column read is also possible by providing its address at each clock cycle. The

multiple bank nature enables interleaving among internal banks to hide the precharging time.

By having a programmable Mode Register, the system can change burst length, latency cycle,

interleave or sequential burst to maximize its performance. W987Z6CB is ideal for main memory in

high performance applications.

2. FEATURES

•

Power supply V

= 2.7V

−

3.6V

•

DDQ

= 2.7V

−

3.6V

•

Standard Self Refresh Mode

•

Power Down Mode

•

CAS Latency: 2 and 3

•

Burst Length: 1, 2, 4, 8, and full page

•

4K Refresh cycles / 64 mS

•

Interface: LVTTL

•

Packaged in 54 balls FBGA

•

Operating Temperature Range

−

Commercial temperature (0° C

−

70° C)

−

Extended temperature (-25° C

−

85° C)

−

Industrial temperature (-40° C

−

85° C)

3. AVAILABLE PART NUMBER

PART NUMBER

W987Z6CBN75

W987Z6CBG75

W987Z6CBN80

W987Z6CBG80

SPEED

133 MHz/CL3

125 MHz/CL3

SELF REFRESH

CURRENT

(MAX.)

400

µA

400

µA

400

µA

400

µA

TEMPERATURE

RANGE

-25° C

−

85° C

-25° C

−

85° C

-25° C

−

85° C

-25° C

−

85° C

LEAD-FREE

PACKAGE

Yes

-3-

Publication Release Date: June 24, 2002

Revision A1

Preliminary W987Z6CB

4. BALL CONFIGURATION

(TOP VIEW )

Vss

DQ15

DQ0

DQ14

DQ13

DQ2

DQ1

DQ12

DQ11

DQ4

DQ3

DQ10

DQ9

DQ6

DQ5

DQ8

LDQM

DQ7

UDQM

CLK

CKE

CAS

RAS

A11

BA0

BA1

A10/

Vss

Package dimension 8mm x 9 mm

-4-

Preliminary W987Z6CB

5. BALL DESCRIPTION

PIN NUMBER

H7, H8, J8, J7,

J3, J2, H3, H2,

H1, G3, H9, G2

G7, G8

A8, B9, B8, C9,

C8, D9, D8, E9,

E1, D2 D1, C2,

C1, B2, B1, A2

BALL NAME

−

A11

FUNCTION

Address

DESCRIPTION

Multiplexed pins for row and column address.

Row address: A0

−

A11. Column address: A0

−

A8.

Select bank to activate during row address latch

time, or bank to read/write during address latch

time.

BS0, BS1

Bank Select

DQ0

−

DQ15

Data Input/

Output

Multiplexed pins for data output and input.

Chip Select

Disable or enable the command decoder. When

command decoder is disabled, new command is

ignored and previous operation continues.

Command input. When sampled at the rising edge

of the clock, RAS , CAS and WE define the

operation to be executed.

Referred to RAS

The output buffer is placed at Hi-Z (with latency of

2) when DQM is sampled high in read cycle. In

write cycle, sampling DQM high will block the write

operation with zero latency.

System clock used to sample inputs on the rising

edge of clock.

CKE controls the clock activation and deactivation.

When CKE is low, Power Down mode, Suspend

mode or Self Refresh mode is entered.

Power for input buffers and logic circuit inside

DRAM.

Ground for input buffers and logic circuit inside

DRAM.

Separated power from V

, used for output buffers

to improve noise.

RAS

Row Address

Strobe

Column

Address

Strobe

Write Enable

Input/Output

Mask

CAS

UDQM

LDQM

CLK

F1, E8

Clock Inputs

CKE

Clock Enable

A9, E7, J9

A1, E3, J1

A7, B3, C7, D3

A3, B7, C3, D7

E2, G1

DDQ

Power

Ground

Power for I/O

Buffer

Ground for I/O Separated ground from V

, used for output

Buffer

buffers to improve noise.

No Connection No connection

-5-

Publication Release Date: June 24, 2002

Revision A1

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W987Z6CBN80 Related Products

	W987Z6CBN80	W987Z6CBG80	W987Z6CBG75	W987Z6CBN75
Description	Synchronous DRAM, 8MX16, 6ns, CMOS, PBGA54, 8 X 9 MM, 1.20 MM HEIGHT, FBGA-54	Synchronous DRAM, 8MX16, 6ns, CMOS, PBGA54, 8 X 9 MM, 1.20 MM HEIGHT, FBGA-54	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54, 8 X 9 MM, 1.20 MM HEIGHT, FBGA-54	Synchronous DRAM, 8MX16, 5.4ns, CMOS, PBGA54, 8 X 9 MM, 1.20 MM HEIGHT, FBGA-54
Maker	Winbond Electronics Corporation	Winbond Electronics Corporation	Winbond Electronics Corporation	Winbond Electronics Corporation
Parts packaging code	BGA	BGA	BGA	BGA
package instruction	TFBGA,	TFBGA,	TFBGA,	TFBGA,
Contacts	54	54	54	54
Reach Compliance Code	compliant	compliant	compliant	compliant
ECCN code	EAR99	EAR99	EAR99	EAR99
access mode	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST	FOUR BANK PAGE BURST
Maximum access time	6 ns	6 ns	5.4 ns	5.4 ns
Other features	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH	AUTO/SELF REFRESH
JESD-30 code	R-PBGA-B54	R-PBGA-B54	R-PBGA-B54	R-PBGA-B54
JESD-609 code	e1	e1	e1	e1
length	9 mm	9 mm	9 mm	9 mm
memory density	134217728 bit	134217728 bit	134217728 bit	134217728 bit
Memory IC Type	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM	SYNCHRONOUS DRAM
memory width	16	16	16	16
Number of functions	1	1	1	1
Number of ports	1	1	1	1
Number of terminals	54	54	54	54
word count	8388608 words	8388608 words	8388608 words	8388608 words
character code	8000000	8000000	8000000	8000000
Operating mode	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS	SYNCHRONOUS
Maximum operating temperature	70 °C	70 °C	70 °C	70 °C
organize	8MX16	8MX16	8MX16	8MX16
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	TFBGA	TFBGA	TFBGA	TFBGA
Package shape	RECTANGULAR	RECTANGULAR	RECTANGULAR	RECTANGULAR
Package form	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH	GRID ARRAY, THIN PROFILE, FINE PITCH
Certification status	Not Qualified	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	1.2 mm	1.2 mm	1.2 mm	1.2 mm
self refresh	YES	YES	YES	YES
Maximum supply voltage (Vsup)	3.6 V	3.6 V	3.6 V	3.6 V
Minimum supply voltage (Vsup)	2.7 V	2.7 V	2.7 V	2.7 V
Nominal supply voltage (Vsup)	3 V	3 V	3 V	3 V
surface mount	YES	YES	YES	YES
technology	CMOS	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal surface	TIN SILVER COPPER	TIN SILVER COPPER	TIN SILVER COPPER	TIN SILVER COPPER
Terminal form	BALL	BALL	BALL	BALL
Terminal pitch	0.8 mm	0.8 mm	0.8 mm	0.8 mm
Terminal location	BOTTOM	BOTTOM	BOTTOM	BOTTOM
width	8 mm	8 mm	8 mm	8 mm

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