VSC7146RH datasheet, PDF - EEWORLD Datasheet

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VSC7146RH: Description2.5Gb/s, 20-Bit Transceiver; CategoryWireless rf/communication Telecom circuit; File Size185KB，19 Pages; ManufacturerVitesse Semiconductor Corporation; Websitehttp://www.vitesse.com/

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VSC7146RH Overview

2.5Gb/s, 20-Bit Transceiver

VSC7146RH Parametric

Parameter Name	Attribute value
Maker	Vitesse Semiconductor Corporation
Parts packaging code	QFP
package instruction	HQFP,
Contacts	80
Reach Compliance Code	unknow
JESD-30 code	S-PQFP-G80
length	14 mm
Number of functions	1
Number of terminals	80
Package body material	PLASTIC/EPOXY
encapsulated code	HQFP
Package shape	SQUARE
Package form	FLATPACK, HEAT SINK/SLUG
Certification status	Not Qualified
Maximum seat height	2.35 mm
Nominal supply voltage	3.3 V
surface mount	YES
Telecom integrated circuit types	TELECOM CIRCUIT
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
width	14 mm

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VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC7146

Features

• Speed Selectable Full-Duplex Transceiver:

- 1.06/2.12Gb/s for FibreChannel

- 1.25/2.5Gb/s for Gigabit Ethernet

• 20-Bit TTL Interface for Transmit and

Receive Data at 125MHz

• Monolithic Clock Synthesis and Clock

Recovery - No External Components

• 125MHz TTL Reference Clock

2.5Gb/s, 20-Bit Transceiver

• Automatic Lock-to-Reference Function

• Suitable for Both Coaxial and Optical Link Appli-

cations

• Low Power Operation: 2.5 W max

• 80-Pin, 14mm Thermally-Enhanced EDQUAD

Package

• Single +3.3V Supply

General Description

The VSC7146 is a 2.5Gb/s Transceiver optimized for ease-of-use and efficiency in high-performance data

transmission systems. The VSC7146 accepts two 10-bit 8b/10b encoded transmit characters, latches them on

the rising edge of Transmit Byte Clock (TBC) and serializes the data onto the TX+/- differential outputs at a

baud rate, which is 20 times the TBC frequency. The VSC7146 also samples serial receive data on the RX+/-

differential inputs, recovers the clock and data, deserializes it onto two 10-bit receive characters, outputs a

recovered clocks at one-twentieth of the incoming baud rate and detects Fibre Channel “comma” characters.

The VSC7146 contains on-chip Phase-Lock Loop (PLL) circuitry for synthesis of the baud-rate transmit clock,

and extraction of the clock from the received serial stream. These circuits are fully monolithic and require no

external components.

Block Diagram

EWRAP

R0:19

Serial to

Parallel

Retimed

Data

Recovered

Clock

Recovery

2:1

RX+

RX-

RBC

RBCN

125 MHz

Comma

Detect

RXRATE

COM_DET

EN_CDET

Frame

Logic

T0:19

TBC

Parallel

to Serial

2.5 Gb/s

Serial Data

2.5 Gb/s

TX+

TX-

125 MHz

REF

TXRATE

BCMN

PLL Clock

Multiply (x20)

2.5 GHz

Synthesized

Clock

G52162-0, Rev. 2.7

8/28/00

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page 1

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

2.5Gb/s, 20-Bit Transceiver

VSC7146

Functional Description

Clock Synthesizer

The VSC7146 clock synthesizer multiplies the 125MHz reference frequency provided on the REF input by

20 to achieve a baud rate clock at 2.5GHz. The clock synthesizer contains a fully monolithic PLL which

requires no external components. An additional 125MHz clock, TBC, should be provided to clock in the data

bus. Since TBC is only used for the purpose of clocking data in, it is not required to have the same jitter

constraints as REF. REF clock and TBC should preserve certain phase margins and be of the same frequency.

Serializer

The VSC7146 accepts TTL input data as two parallel 10-bit characters on the T[0:19] bus which is latched

into the input latch on the rising edge of a 125MHz clock at TBC. This data will be serialized and transmitted on

the TX differential outputs at a baud rate of 20 times the frequency of the TBC input, with bit T0 transmitted

first. User data should be encoded for transmission using the 8B/10B block code described in the Fibre Channel

specification, or an equivalent, edge rich, DC-balanced code. If EWRAP is HIGH, the transmitter will be

disabled with TX+ HIGH and TX- LOW. If EWRAP is LOW, the transmitter outputs serialized data. The

phases of REF clock and TBC can be identical, but there is a phase relationship between the two input clocks

which must be maintained.

Transmission Character Interface

In Fibre Channel, an encoded byte is 10 bits and is referred to as a transmission character. The 20-bit

interface on the VSC7146 corresponds to two transmission characters. This mapping is shown in Figure 1.

Figure 1: Transmission Order and Mapping to Fibre Channel Character

Parallel Data Bits

8B/10B Bit Position

Valid “Comma” Position

Last Data Bit Transmitted

First Data Bit Transmitted

Clock Recovery

The VSC7146 accepts differential high-speed serial inputs on the RX+/RX- pins, (when EWRAP is LOW),

extracts the clock and retimes the data. The serial bit stream should be encoded so as to provide DC balance and

limited run length by a Fibre Channel-compatible 8B/10B transmitter or equivalent. The VSC7146 clock

recovery circuitry is completely monolithic and requires no external components. For proper operation, the

baud rate of the data stream to be recovered should be within 200ppm of twenty times the REF frequency. This

allows oscillators on either end of the link to be 125MHz +/- 100ppm.

Page 2

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52162-0 Rev. 2.7

8/28/00

VITESSE

SEMICONDUCTOR CORPORATION

Advance Product Information

VSC7146

2.5Gb/s, 20-Bit Transceiver

Deserializer

The retimed serial bit stream is converted into two 10-bit parallel output characters. The VSC7146 provides

a TTL recovered clock, RBC, at one twentieth of the serial baud rate. The clock is generated by dividing down

the high-speed clock which is phase-locked to the serial data. The serial data is retimed by the internal high-

speed clock, and deserialized. The resulting parallel data will be captured by the adjoining protocol logic on the

rising edge of RBC.

If serial input data is not present, or does not meet the required baud rate, the VSC7146 will continue to

produce a recovered clock and RBC will automatically lock to the REF reference clock. This eliminates the

need for a Lock-to-Reference input pin and simplifies the support software for that function.

Word Alignment

The VSC7146 provides 7-bit Fibre Channel “comma” character recognition and data word alignment. Word

synchronization is enabled by asserting EN_CDET HIGH. When synchronization is enabled, the VSC7146

constantly examines the serial data for the presence of the Fibre Channel “comma” character. This pattern is

“0011111XXX”, where the leading zero corresponds to the first bit received. The “comma” sequence is not

contained in any normal 8B/10B coded data character or pair of adjacent characters. It occurs only within

special characters, known as K28.1, K28.5 and K28.7, which are defined specifically for synchronization in

Fibre Channel systems. Improper alignment of the “comma” character is defined as either of the following

conditions:

1) The “comma” is not aligned within the 10-bit transmission character such that T0...T6 = “0011111.”

2) The “comma” straddles the boundary between two 10-bit transmission characters.

When EN_CDET is HIGH and an improperly aligned “comma” is encountered, the internal data is shifted

in such a manner that the “comma” character is aligned properly in R[0:6] as shown in Figure 1. This results in

proper character and word alignment. When the parallel data alignment changes in response to a improperly

aligned “comma” pattern, some data which would have been presented on the parallel output port may be lost.

However, the synchronization character and subsequent data will be output correctly and properly aligned.

When EN_CDET is LOW, the current alignment of the serial data is maintained indefinitely, regardless of data

pattern.

On encountering a “comma” character, COM_DET is driven HIGH to inform the user that realignment of

the parallel data field may have occurred. The COM_DET pulse is presented simultaneously with the “comma”

character and has a duration equal to the data. The COM_DET signal is timed such that it can be captured by the

adjoining protocol logic on the rising edge of RBC. Functional waveforms for synchronization are shown in

Figure 2 and Figure 3. Figure 2 shows the case when a “comma” character is detected and no phase adjustment

is necessary. It illustrates the position of the COM_DET pulse in relation to the “comma” character on R[0:6].

Figure 3 shows the case where the K28.5 is detected, but it is out-of-phase and a change in the output data

alignment is required. Note that up to three characters prior to the “comma” character may be corrupted by the

realignment process.

G52162-0, Rev. 2.7

8/28/00

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page 3

VSC7146RH Related Products

	VSC7146RH	VSC7146
Description	2.5Gb/s, 20-Bit Transceiver	2.5Gb/s, 20-Bit Transceiver

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