W1D128M72R8B-5AL-PA2 datasheet, PDF

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W1D128M72R8B-5AL-PA2: Description128MX8 DDR DRAM MODULE, 0.5ns, DMA240, MO-237, DIMM-240; Categorystorage storage; File Size255KB，11 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

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W1D128M72R8B-5AL-PA2 Overview

128MX8 DDR DRAM MODULE, 0.5ns, DMA240, MO-237, DIMM-240

W1D128M72R8B-5AL-PA2 Parametric

Parameter Name	Attribute value
Maker	XILINX
Parts packaging code	DIMM
package instruction	DIMM,
Contacts	240
Reach Compliance Code	unknown
access mode	SINGLE BANK PAGE BURST
Maximum access time	0.5 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-XDMA-N240
JESD-609 code	e4
length	133.35 mm
memory density	1073741824 bit
Memory IC Type	DDR DRAM MODULE
memory width	8
Number of functions	1
Number of ports	1
Number of terminals	240
word count	134217728 words
character code	128000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	55 °C
Minimum operating temperature
organize	128MX8
Package body material	UNSPECIFIED
encapsulated code	DIMM
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Certification status	Not Qualified
Maximum seat height	2.7 mm
Maximum supply voltage (Vsup)	1.9 V
Minimum supply voltage (Vsup)	1.7 V
Nominal supply voltage (Vsup)	1.8 V
surface mount	NO
Temperature level	COMMERCIAL
Terminal surface	GOLD
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	DUAL
width	25.4 mm

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DDR2-400, 533

Single Rank, x8 Registered SDRAM DIMMs

256MB

512MB

1GB

2GB

W1D32M72R8

W1D64M72R8

W1D128M72R8

W1D256M72R8 (Preliminary*)

Figure 1: Available layouts

Layout A:

1.181"

Features:

•

240-pin Registered ECC DDR2 SDRAM Dual-In-

Line Memory Module for DDR2-400 and DDR2-533

JEDEC standard VDD=1.8V (+/- 0.1V) power

supply

One rank 256MB, 512MB, 1GB, and 2GB

Modules are built with 18 x8 DDR2 SDRAM

devices in a 60-ball FBGA package

ECC error detection and correction

Programmable CAS Latency of 3 and 4; Burst

Length of 4 and 8

Auto Refresh and Self Refresh Mode

OCD (Off-Chip Driver Impedance Adjustment) and

ODT (On-Die Termination)

SPD (Serial Presence Detect) with EEPROM

All input/output are SSTL_18 compatible

All contacts are gold plated

One clock delay for register

Layout B:

1.0"

Front view of double-sided DIMM (see detail physical dimensions

at the back)

Speed Grades:

-5

-3.75

Units

Module Speed Grade

PC2-3200 PC2-4200

Speed @ CL3

400

MHz

Speed @ CL4

400

533

MHz

Speed @ CL5

533

MHz

Note: See Product ordering for full naming guide

Speed Grade

Description:

The following specification covers the W1D32M72R8, W1D64M72R8, W1D128M72R8, and W1D256M72R8

family of Single-Rank Registered ECC DDR2 modules using x8 FBGA SDRAMs. Please reference Figure 1 for

available layout configurations and the product ordering guide on the final page of this specification for available

options including speed grade and silicon manufacturer.

Address Summary Table:

Module Configuration

Refresh

Device Configuration

Row Addressing

Column Addressing

Module Rank

256MB

32M x 72

32M x 8

(9 components)

A0-A13

A0-A9

512MB

64M x 72

64M x 8

(9 components)

A0-A13

A0-A9

1GB

128M x 72

128M x 8

(9 components)

A0-A14

A0-A9

2GB

256M x 72

256M x 8

(9 components)

A0-A14

A0-A9

*Specifications are for reference purposes only and are subject to change by Wintec without notice.

DDR2_RDIMM_1 rank_x8_spec

Rev. 1.0 - December, 04

Wintec Industries, Inc., reserves the right to change datasheets and/or products without any notice.



2004 Wintec Industries, Inc.

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