10
Spartan-6 Family Overview
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General Description
The Spartan®-6 family provides leading system integration capabilities with the lowest total cost for high-volume applications. The
thirteen-member family delivers expanded densities ranging from 3,840 to 147,443 logic cells, with half the power consumption of previous
Spartan families and faster, more comprehensive connectivity. Built on a mature 45 nm low-power copper process technology that delivers
the optimal balance of cost, power, and performance, the Spartan-6 family offers a new, more efficient, dual-register 6-input look-up table
(LUT) logic and a rich selection of built-in system-level blocks. These include 18 Kb (2 x 9 Kb) block RAMs, second generation DSP48A1
slices, SDRAM memory controllers, enhanced mixed-mode clock management blocks, SelectIO™ technology, power-optimized high-
speed serial transceiver blocks, PCI Express™ compatible Endpoint blocks, advanced system-level power management modes, auto-
detect configuration options, and enhanced IP security with AES and Device DNA protection. These features provide a low-cost
programmable alternative to custom ASIC products with unprecedented ease-of-use. Spartan-6 FPGAs offer the best solution for high-
volume logic designs, consumer-oriented DSP designs, and cost-sensitive embedded applications. Spartan-6 FPGAs are the
programmable silicon foundation for Targeted Design Platforms that deliver integrated software and hardware components to enable
designers to focus on innovation as soon as their development cycle begins.
Summary of Spartan-6 FPGA Features
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Spartan-6 Family:
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Spartan-6 LX FPGA: Logic optimized
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Spartan-6 LXT FPGA: High-speed serial connectivity
Designed for low cost
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Multiple efficient integrated blocks
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Optimized selection of I/O standards
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Staggered pads
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High volume plastic wire-bonded packages
Low static and dynamic power
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45 nm process optimized for cost and low power
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Hibernate power-down mode for zero power
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Suspend mode maintains state and configuration with
multi-pin wake-up, control enhancement
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Lower-power 1.0V core voltage (LX FPGAs, -1L only)
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High performance 1.2V core voltage (LX and LXT
FPGAs, -2, -3, and -4 speed grades)
Multi-voltage, multi-standard SelectIO banks
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Up to 1050 Mb/s data transfer rate per differential I/O
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Selectable output drive, up to 24 mA per pin
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3.3V to 1.2V I/O standards and protocols
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Low-cost HSTL and SSTL memory interfaces
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Hot swap compliance
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Adjustable I/O slew rates to improve signal integrity
High-speed GTP serial transceivers in the LXT FPGAs
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Up to 3.125 Gb/s
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High speed interfaces including: Serial ATA, Aurora,
1G Ethernet, PCI Express, OBSAI, CPRI, EPON,
GPON, DisplayPort, and XAUI
Integrated Endpoint block for PCI Express designs (LXT)
Low-cost PCI® technology support compatible with the
33 MHz, 32- and 64-bit specification.
Efficient DSP48A1 slices
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High-performance arithmetic and signal processing
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Fast 18 x 18 multiplier and 48-bit accumulator
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Pipelining and cascading capability
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Pre-adder to assist filter applications
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Integrated Memory Controller blocks
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DDR, DDR2, DDR3, and LPDDR support
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Data rates up to
800 Mb/s (12.8
Gb/s peak bandwidth)
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Multi-port bus structure with independent FIFO to reduce
design timing issues
Abundant logic resources with increased logic capacity
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Optional shift register or distributed RAM support
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Efficient 6-input LUTs improve performance and
minimize power
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LUT with dual flip-flops for pipeline centric applications
Block RAM with a wide range of granularity
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Fast block RAM with byte write enable
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18 Kb blocks that can be optionally programmed as two
independent 9 Kb block RAMs
Clock Management Tile (CMT) for enhanced performance
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Low noise, flexible clocking
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Digital Clock Managers (DCMs) eliminate clock skew
and duty cycle distortion
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Phase-Locked Loops (PLLs) for low-jitter clocking
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Frequency synthesis with simultaneous multiplication,
division, and phase shifting
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Sixteen low-skew global clock networks
Simplified configuration, supports low-cost standards
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2-pin auto-detect configuration
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Broad third-party SPI (up to x4) and NOR Flash support
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Feature rich Xilinx Platform Flash with JTAG
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MultiBoot support for remote upgrade with multiple
bitstreams, using watchdog protection
Enhanced security for design protection
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Unique Device DNA identifier for design authentication
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AES bitstream encryption in the larger devices
Faster embedded processing with enhanced, low cost,
MicroBlaze™ soft processor
Industry-leading IP and reference designs
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© 2009 Xilinx, Inc. XILINX, the Xilinx logo, Virtex, Spartan, ISE, and other designated brands included herein are trademarks of Xilinx in the United States and other countries.
PCI, PCIe and PCI Express are trademarks of PCI-SIG and used under license. All other trademarks are the property of their respective owners.
DS160 (v1.3) November 5, 2009
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Spartan-6 Family Overview
Spartan-6 FPGA Feature Summary
Table 1:
Spartan-6 FPGA Feature Summary by Device
Configurable Logic Blocks (CLBs)
Device
Logic
Cells
(1)
Slices
(2)
Max
Flip-Flops Distributed
RAM (Kb)
DSP48A1
Slices
(3)
Block RAM Blocks
18 Kb
(4)
CMTs
(5)
Max (Kb)
Memory
Endpoint
Maximum
Total Max
Controller
Blocks for
GTP
I/O
User
Blocks
PCI Express Transceivers Banks I/O
(Max)
XC6SLX4
XC6SLX9
XC6SLX16
XC6SLX25
XC6SLX45
XC6SLX75
XC6SLX100
XC6SLX150
XC6SLX25T
XC6SLX45T
XC6SLX75T
XC6SLX100T
XC6SLX150T
3,840
9,152
14,579
24,051
43,661
74,637
101,261
147,443
24,051
43,661
74,637
101,261
147,443
600
1,430
2,278
3,750
6,822
11,662
15,822
23,038
3,750
6,822
11,662
15,822
23,038
4,800
11,440
18,224
30,064
54,576
93,296
126,576
184,304
30,064
54,576
93,296
126,576
184,304
75
90
136
229
401
692
976
1,355
229
401
692
976
1,355
8
16
32
38
58
132
180
180
38
58
132
180
180
12
32
32
52
116
172
268
268
52
116
172
268
268
216
576
576
936
2,088
3,096
4,824
4,824
936
2,088
3,096
4,824
4,824
2
2
2
2
4
6
6
6
2
4
6
6
6
0
2
2
2
2
4
4
4
2
2
4
4
4
0
0
0
0
0
0
0
0
1
1
1
1
1
0
0
0
0
0
0
0
0
2
4
8
8
8
4
4
4
4
4
6
6
6
4
4
6
6
6
132
200
232
266
358
408
480
576
250
296
348
498
540
Notes:
1.
2.
3.
4.
5.
Spartan-6 FPGA logic cell ratings reflect the increased logic cell capability offered by the new 6-input LUT architecture.
Each Spartan-6 FPGA slice contains four LUTs and eight flip-flops.
Each DSP48A1 slice contains an 18 x 18 multiplier, an adder, and an accumulator.
Block RAMs are fundamentally 18 Kb in size. Each block can also be used as two independent 9 Kb blocks.
Each CMT contains two DCMs and one PLL.
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Spartan-6 Family Overview
Spartan-6 FPGA Device-Package Combinations and Available I/Os
Spartan-6 FPGA package combinations with the available I/Os and GTP transceivers per package are shown in
Table 2.
Due to the transceivers, the LX and LXT pinouts are not compatible.
Table 2:
Spartan-6 Device-Package Combinations and Maximum Available I/Os
Package CPG196
(1)
Size (mm)
Pitch (mm)
Device
XC6SLX4
XC6SLX9
XC6SLX16
XC6SLX25
XC6SLX45
XC6SLX75
XC6SLX100
XC6SLX150
XC6SLX25T
XC6SLX45T
XC6SLX75T
XC6SLX100T
XC6SLX150T
2
4
190
190
8x8
0.5
User I/O
TQG144
(1)
20 x 20
0.5
User I/O
CSG225
(2)
13 x 13
0.8
User I/O
FT(G)256
(3)
17 x 17
1.0
User I/O
CSG324
15 x 15
0.8
GTPs
User
I/O
FG(G)484
(3,4)
23 x 23
1.0
GTPs
User
I/O
CSG484
(4)
19 x 19
0.8
GTPs
User
I/O
FG(G)676
(3)
27 x 27
1.0
GTPs
User
I/O
FG(G)900
(3)
31 x 31
1.0
GTPs
User
I/O
106
106
106
102
102
132
160
160
186
186
186
NA
NA
NA
NA
200
232
226
218
NA
NA
NA
NA
NA
2
4
4
4
4
266
316
280
326
338
250
296
268
296
296
4
4
4
4
296
292
296
296
8
8
8
348
376
396
8
8
498
540
NA
NA
NA
NA
320
328
338
338
NA
NA
NA
NA
358
408
480
498
NA
576
Notes:
1. There is no memory controller on the devices in these packages.
2. Memory controller block support is x8 on the XC6SLX9 and XC6SLX16 devices. There is no memory controller in the XC6SLX4.
3. These devices are available in both Pb and Pb-free (additional G) packages as standard ordering options.
4. These packages support two of the four memory controllers in the XC6SLX75, XC6SLX75T, XC6SLX100, XC6SLX100T, XC6SLX150, and
XC6SLX150T devices.
Configuration
Spartan-6 FPGAs store the customized configuration data in SRAM-type internal latches. The number of configuration bits
is between 2.6 Mb and 33 Mb depending on device size but independent of the specific user-design implementation, unless
compression mode is used. The configuration storage is volatile and must be reloaded whenever the FPGA is powered up.
This storage can also be reloaded at any time by pulling the PROGRAM_B pin Low. Several methods and data formats for
loading configuration are available.
Bit-serial configurations can be either master serial mode, where the FPGA generates the configuration clock (CCLK) signal,
or slave serial mode, where the external configuration data source also clocks the FPGA. For byte-wide configurations,
master SelectMAP mode generates the CCLK signal while slave SelectMAP mode receives the CCLK signal for the 8- and
16-bit-wide transfer. In master serial mode, the beginning of the bitstream can optionally switch the clocking source to an
external clock, which can be faster or more precise than the internal clock. The available JTAG pins use boundary-scan
protocols to load bit-serial configuration data.
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Spartan-6 Family Overview
The bitstream configuration information is generated by the ISE™ software using a program called BitGen. The
configuration process typically executes the following sequence:
•
•
•
•
•
Detects power-up (power-on reset) or PROGRAM_B when Low.
Clears the whole configuration memory.
Samples the mode pins to determine the configuration mode: master or slave, bit-serial or parallel.
Loads the configuration data starting with the bus-width detection pattern followed by a synchronization word, checks
for the proper device code, and ends with a cyclic redundancy check (CRC) of the complete bitstream.
Starts a user-defined sequence of events: releasing the internal reset (or preset) of flip-flops, optionally waiting for the
DCMs and/or PLLs to lock, activating the output drivers, and transitioning the DONE pin to High.
Spartan-6 FPGAs support MultiBoot configuration, where two or more FPGA configuration bitstreams can be stored by a
single configuration source. The FPGA application controls which configuration to load next and when to load it.
Spartan-6 FPGAs also include a unique, factory-programmed Device DNA identifier useful for tracking purposes, anti-
cloning designs, or IP protection. In the largest devices, bitstreams can be copy protected using AES encryption.
Dynamic Reconfiguration Port
The dynamic reconfiguration port (DRP) gives the system designer easy access to configuration bits and status registers for
the GTP transceivers.
The DRP behaves like memory-mapped registers, and can access and modify block-specific configuration bits as well as
status and control registers.
Readback
Most configuration data can be read back without affecting the system’s operation.
CLBs, Slices, and LUTs
Each configurable logic block (CLB) in Spartan-6 FPGAs consists of two slices, arranged side-by-side as part of two vertical
columns. There are three types of CLB slices in the Spartan-6 architecture: SLICEM, SLICEL, and SLICEX. Each slice
contains four LUTs, eight flip-flops, and miscellaneous logic. The LUTs are for general-purpose combinatorial and
sequential logic support. Synthesis tools take advantage of these highly efficient logic, arithmetic, and memory features.
Expert designers can also instantiate them.
SLICEM
One quarter (25%) of Spartan-6 slices are SLICEMs. Each of the four SLICEM LUTs can be configured as either a 6-input
LUT with one output, or as dual 5-input LUTs with identical 5-bit addresses and two independent outputs. These LUTs can
also be used as distributed 64-bit RAM with 64 bits or two times 32 bits per LUT, as a single 32-bit shift register (SRL32), or
as two 16-bit shift registers (SRL16s) with addressable length. Each LUT output can be registered in a flip-flop within the
CLB. For arithmetic operations, a high-speed carry chain propagates carry signals upwards in a column of slices.
SLICEL
One quarter (25%) of Spartan-6 slices are SLICELs, which contain all the features of the SLICEM except the memory/shift
register function.
SLICEX
One half (50%) of Spartan-6 slices are SLICEXs. The SLICEXs have the same structure as SLICELs except the arithmetic
carry option and the wide multiplexers.
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Spartan-6 Family Overview
Clock Management
Each Spartan-6 FPGA has up to six CMTs, each consisting of two DCMs and one PLL, which can be used individually or
concatenated.
DCM
The DCM provides four phases of the input frequency (CLKIN): shifted 0°, 90°, 180°, and 270° (CLK0, CLK90, CLK180, and
CLK270). It also provides a doubled frequency CLK2X and its complement CLK2X180. The CLKDV output provides a
fractional clock frequency that can be phase-aligned to CLK0. The fraction is programmable as every integer from 2 to 16,
as well as 1.5, 2.5, 3.5 . . . 7.5. CLKIN can optionally be divided by 2. The DCM can be a zero-delay clock buffer when a clock
signal drives CLKIN, while the CLK0 output is fed back to the CLKFB input.
Frequency Synthesis
Independent of the basic DCM functionality, the frequency synthesis outputs CLKFX and CLKFX180 can be programmed to
generate any output frequency that is the DCM input frequency (F
IN
) multiplied by M and simultaneously divided by D, where
M can be any integer from 2 to 32 and D can be any integer from 1 to 32.
Phase Shifting
With CLK0 connected to CLKFB, all nine CLK outputs (CLK0, CLK90, CLK180, CLK270, CLK2X, CLK2X180, CLKDV,
CLKFX, and CLKFX180) can be shifted by a common amount, defined as any integer multiple of a fixed delay. A fixed DCM
delay value (fraction of the input period) can be established by configuration and can also be incremented or decremented
dynamically.
Spread-Spectrum Input
The DCM can accept and track typical spread-spectrum clock inputs, provided they abide by the input clock specifications
listed in the Spartan-6 data sheet.
PLLs
The PLL can serve as a frequency synthesizer for a wider range of frequencies and as a jitter filter for incoming clocks in
conjunction with the DCMs. The heart of the PLL is a voltage-controlled oscillator (VCO) with a frequency range of
400 MHz to 1000 MHz, thus spanning more than one octave. Three sets of programmable frequency dividers (D, M, and O)
adapt the VCO to the required application.
The pre-divider D (programmable by configuration) reduces the input frequency and feeds one input of the traditional PLL
phase comparator. The feedback divider (programmable by configuration) acts as a multiplier because it divides the VCO
output frequency before feeding the other input of the phase comparator. D and M must be chosen appropriately to keep the
VCO within its controllable frequency range.
The VCO has eight equally spaced outputs (0°, 45°, 90°, 135°, 180°, 225°, 270°, and 315°). Each can be selected to drive
one of the six output dividers, O0 to O5 (each programmable by configuration to divide by any integer from 1 to 128).
Clock Distribution
Each Spartan-6 FPGA provides abundant clock lines to address the different clocking requirements of high fanout, short
propagation delay, and extremely low skew.
Global Clock Lines
In each Spartan-6 FPGA, 16 global-clock lines have the highest fanout and can reach every flip-flop clock. Global clock lines
must be driven by global clock buffers, which can also perform glitchless clock multiplexing and the clock enable function.
Global clocks are often driven from the CMTs, which can completely eliminate the basic clock distribution delay.
I/O Clocks
I/O clocks are especially fast and serve only the localized input and output delay circuits and the I/O serializer/deserializer
(SERDES) circuits, as described in the
I/O Logic
section.
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