0
R
XCR3128XL 128 Macrocell
Automotive IQ CPLD
0
14
DS119-2 (v1.1) October 18, 2004
Advance Product Specification
dard CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor,
Synopsys, ViewLogic, and Synplicity), using text (ABEL,
VHDL, Verilog) and schematic capture design entry. Design
verification uses industry standard simulators for functional
and timing simulation. Development is supported on per-
sonal computer, Sparc, and HP platforms.
The XCR3128XL-Q features also include industry-stan-
dard, IEEE 1149.1, JTAG interface through which bound-
ary-scan testing and In-System Programming (ISP) and
reprogramming of the device can occur. This device is elec-
trically reprogrammable using industry standard device
programmers.
Features
•
•
•
•
Guaranteed to meet full electrical specifications over T
A
= –40°C to +125°C
Technology: 0.35 µm EEPROM process
Full Boundary Scan Test (IEEE 1149.1) for flexible
in-system device and system testing
Fast programming times in production saves time and
money
- Increases system reliability through reduced device
handling
High-speed pin-to-pin delays of 10 ns (100 MHz)
Slew rate control per output to reduce EMI
100% routable which enables all device resources to
be utilized
Refer to XPLA3 Family data sheet (DS012) for
architecture description
Refer to XCR3128XL data sheet (DS016) for pin
descriptions
•
•
•
•
•
Table 1:
CoolRunner XCR3128XL-Q
XCR3128XL-Q
Macrocells
Usable Gates
Registers
F
SYSTEM
(MHz)
User I/O (100-pin VQFP)
User I/O (144-pin TQFP)
70
60
Typical ICC (mA)
50
40
30
20
10
0
0
20
40
60
80
100
Frequency (MHz)
120
140
128
3,000
128
95
84
108
Description
The CoolRunner™ XCR3128XL-Q CPLD Automotive IQ
product is targeted for low power systems that include por-
table, handheld, automotive, and power sensitive applica-
tions. This device includes Fast Zero Power (FZP) design
technology that combines low power and high speed. With
this design technique, the XCR3128XL-Q delivers low
standby current without the need for "turbo bits" or other
power down schemes. By replacing conventional sense
amplifier methods for implementing product terms (a tech-
nique that has been used in PLDs since the bipolar era) with
a cascaded chain of pure CMOS gates, the dynamic power
is also substantially lower than any other CPLD. CoolRun-
ner devices are the only TotalCMOS PLDs, as they use both
a CMOS process technology and the patented full CMOS
FZP design technique.
The CoolRunner XCR3128XL-Q employs a full PLA struc-
ture for logic allocation within a functon block. The PLA pro-
vides maximum flexibility and logic density, with superior pin
locking capability, while maintaining deterministic timing.
The CoolRunner XCR3128XL-Q is supported by Web-
PACK™ and WebFITTER™ from Xilinx and industry stan-
DS016_02_112100
Figure 1:
Typical I
CC
vs. Frequency at V
CC
= 3.3V, 25° C
Table 2:
Typical I
CC
vs. Frequency at V
CC
= 3.3V, 25° C
Frequency (MHz)
Typical I
CC
(mA)
0
0.02
1
0.5
5
2.2
10
4.4
20
8.7
40
17.1
60
25.3
80
33.6
100
41.6
120
49.7
140
57.7
© 2003 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at
http://www.xilinx.com/legal.htm.
All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice.
DS119-2 (v1.1) October 18, 2004
Advance Product Specification
www.xilinx.com
1-800-255-7778
1
XCR3128XL 128 Macrocell Automotive IQ CPLD
R
Absolute Maximum Ratings
(1)
Symbol
V
CC
V
I
I
OUT
T
J
T
STR
Parameter
Supply voltage
(2)
relative to GND
Input voltage
(3)
relative to GND
Output current, per pin
Maximum junction temperature
Storage temperature
Min.
–0.5
–0.5
–100
–40
–65
Max.
4.0
5.5
(4)
100
150
150
Unit
V
V
mA
°
C
°
C
Notes:
1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional
operation at these or any other condition above those indicated in the operational and programming specification is not implied.
2. The chip supply voltage must rise monotonically.
3. Maximum DC undershoot below GND must be limited to either 0.5V or 10 mA, whichever is easier to achieve. During transitions, the
device pins may undershoot to –2.0V or overshoot to 7.0V, provided this over- or undershoot lasts less than 10 ns and with the
forcing current being limited to 200 mA.
4. External I/O voltage may not exceed V
CC
by 4.0V.
Recommended Operating Conditions
Symbol
T
A
V
CC
V
IL
V
IH
V
O
T
R
T
F
Ambient temperature
Supply voltage
Low-level input voltage
High-level input voltage
Output voltage
Input rise time
Input fall time
Parameter
Min.
–40
3.0
0
2.0
0
-
-
Max.
+125
3.6
0.8
5.5
V
CC
20
20
Unit
°C
V
V
V
V
ns
ns
Quality and Reliability Characteristics
Symbol
T
DR
N
PE
Data retention
Program/erase cycles (Endurance) @ T
A
= 70°C
Parameter
Min
20
10,000
Max
-
-
Units
Years
Cycles
2
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DS119-2 (v1.1) October 18, 2004
Advance Product Specification
R
XCR3128XL 128 Macrocell Automotive IQ CPLD
DC Electrical Characteristics Over Recommended Operating Conditions
Symbol
V
OH(1)
V
OL
I
IL(3)
I
IH(3)
I
CCSB
I
CC
C
IN
C
CLK
C
I/O
Parameter
Output High voltage
Test Conditions
I
OH
= –500
µA
V
CC
= 3.0V, I
OH
= –8 mA
Output Low voltage
Input leakage current
I/O High-Z leakage current
Standby current
Dynamic current
(4)
I
OL
= 8 mA
V
IN
= GND or V
CC
V
IN
= GND or V
CC
V
CC
= 3.6V
f = 1 MHz
f = 50 MHz
Input pin capacitance
(5)
Clock input capacitance
(5)
I/O pin capacitance
(5)
f = 1 MHz
f = 1 MHz
f = 1 MHz
Min.
90%V
CC(2)
2.4
-
–10
–10
-
-
-
-
-
-
Max.
-
-
0.4
10
10
5.0
10.0
50.0
8.0
12.0
10.0
Unit
V
V
V
µA
µA
mA
mA
mA
pF
pF
pF
Notes:
1. See
Figure 2
for output drive characteristics of the XPLA3 family.
2. This parameter guaranteed by design and characterization, not by testing.
3. Typical leakage current is less than 1
µA.
4. This parameter measured with a 16-bit, resetable up/down counter loaded into every function block, with all outputs disabled and
unloaded. Inputs are tied to V
CC
or ground. This parameter guaranteed by design and characterization, not testing.
5. Typical values, not tested.
100
90
80
70
60
I
OL
(3.3V)
mA
50
40
30
20
10
0
0
0.5
1
1.5
2
2.5
3
3.5
4
4.5
5
I
OH
(2.7V)
I
OH
(3.3V)
Volts
DS012_10_040402
Figure 2:
Typical I/V Curve for the XPLA3 Family, 25°C
DS119-2 (v1.1) October 18, 2004
Advance Product Specification
www.xilinx.com
1-800-255-7778
3
XCR3128XL 128 Macrocell Automotive IQ CPLD
R
AC Electrical Characteristics Over Recommended Operating Conditions
(1)
-10
Symbol
T
PD1
T
PD2
T
CO
T
SUF
T
SU1(2)
T
SU2
T
H(2)
T
WLH(2)
T
PLH(2)
T
R(2)
T
L(2)
f
SYSTEM(2)
T
CONFIG(2)
T
INIT
T
POE(2)
T
POD(2)
T
PCO(2)
T
PAO(2)
Parameter
Propagation delay time (single p-term)
Propagation delay time (OR array)
Clock to output (global synchronous pin clock)
Setup time (fast input register)
Setup time (single p-term)
Setup time (OR array)
Hold time
Global Clock pulse width (High or Low)
P-term clock pulse width
Input rise time
Input fall time
Maximum system frequency
Configuration time
(3)
ISP initialization time
P-term OE to output enabled
P-term OE to output disabled
(4)
P-term clock to output
P-term set/reset to output valid
Min.
-
-
-
3.0
5.4
6.3
0.0
4.0
6.0
-
-
-
-
-
-
-
-
-
Max.
9.1
10
6.5
-
-
-
-
-
-
20.0
20.0
95
100
100
11.2
11.2
10.7
11.2
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
µs
µs
ns
ns
ns
ns
Notes:
1. Specifications measured with one output switching.
2. These parameters guaranteed by design and/or characterization, not testing.
3. Typical current draw during configuration is 3 mA at 3.6V.
4. Output C
L
= 5 pF.
4
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DS119-2 (v1.1) October 18, 2004
Advance Product Specification
R
XCR3128XL 128 Macrocell Automotive IQ CPLD
Internal Timing Parameters
(1)
-10
Symbol
Buffer Delays
T
IN
T
FIN
T
GCK
T
OUT
T
EN
T
LDI
T
SUI
T
HI
T
ECSU
T
ECHO
T
COI
T
AOI
T
RAI
T
PTCK
T
LOGI1
T
LOGI2
T
F
T
LOGI3
T
UDA
T
SLEW
Input buffer delay
Fast Input buffer delay
Global Clock buffer delay
Output buffer delay
Output buffer enable/disable delay
-
-
-
-
-
2.2
3.1
1.3
3.6
5.7
ns
ns
ns
ns
ns
Parameter
Min.
Max.
Unit
Internal Register, Product Term, and Combinatorial Delays
Latch transparent delay
Register setup time
Register hold time
Register clock enable setup time
Register clock enable hold time
Register clock to output delay
Register async. S/R to output delay
Register async. recovery
Product term clock delay
Internal logic delay (single p-term)
Internal logic delay (PLA OR term)
-
1.2
0.7
3.0
5.5
-
-
-
-
-
-
2.0
-
-
-
-
1.6
2.1
6.0
3.3
3.3
4.2
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Feedback Delays
ZIA delay
-
3.5
ns
Time Adders
Fold-back NAND delay
Universal delay
Slew rate limited delay
-
-
-
3.0
2.7
6.0
ns
ns
ns
Notes:
1. These parameters guaranteed by design and characterization, not testing.
DS119-2 (v1.1) October 18, 2004
Advance Product Specification
www.xilinx.com
1-800-255-7778
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