XCR5064-12PQ100I datasheet, PDF

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XCR5064-12PQ100I: DescriptionEE PLD, 12ns, 64-Cell, CMOS, PQFP100, PLASTIC, QFP-100; CategoryProgrammable logic devices Programmable logic; File Size252KB，14 Pages; ManufacturerXILINX; Websitehttps://www.xilinx.com/

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XCR5064-12PQ100I Overview

EE PLD, 12ns, 64-Cell, CMOS, PQFP100, PLASTIC, QFP-100

XCR5064-12PQ100I Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	XILINX
Parts packaging code	QFP
package instruction	PLASTIC, QFP-100
Contacts	100
Reach Compliance Code	not_compliant
Other features	NO
maximum clock frequency	67 MHz
In-system programmable	NO
JESD-30 code	R-PQFP-G100
JESD-609 code	e0
JTAG BST	NO
length	20 mm
Humidity sensitivity level	3
Dedicated input times	2
Number of I/O lines	64
Number of macro cells	64
Number of terminals	100
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
organize	2 DEDICATED INPUTS, 64 I/O
Output function	MACROCELL
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP100,.7X.9
Package shape	RECTANGULAR
Package form	FLATPACK
power supply	5 V
Programmable logic type	EE PLD
propagation delay	12 ns
Certification status	Not Qualified
Maximum seat height	3.4 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	0.65 mm
Terminal location	QUAD
width	14 mm

XCR5064-12PQ100I Preview

This product has been discontinued. Please see

www.xilinx.com/partinfo/notify/pdn0007.htm

for details.



XCR5064: 64 Macrocell CPLD

14*

DS043 (v1.3) October 9, 2000

Product Specification

CPLD. These devices are the first TotalCMOS PLDs, as

they use both a CMOS process technology

and

the pat-

ented full CMOS FZP design technique. For 3V applica-

tions, Xilinx also offers the high speed PZ3064 CPLD that

offers these features in a full 3V implementation.

The Xilinx FZP CPLDs utilize the patented XPLA

(eXtended Programmable Logic Array) architecture. The

XPLA architecture combines the best features of both PLA

and PAL type structures to deliver high speed and flexible

logic allocation that results in superior ability to make

design changes with fixed pinouts. The XPLA structure in

each logic block provides a fast 7.5 ns PAL path with five

dedicated product terms per output. This PAL path is joined

by an additional PLA structure that deploys a pool of 32

product terms to a fully programmable OR array that can

allocate the PLA product terms to any output in the logic

block. This combination allows logic to be allocated effi-

ciently throughout the logic block and supports as many as

37 product terms on an output. The speed with which logic

is allocated from the PLA array to an output is only 2.0 ns,

regardless of the number of PLA product terms used, which

results in worst case t

’s of only 9.5 ns from any pin to any

other pin. In addition, logic that is common to multiple out-

puts can be placed on a single PLA product term and

shared across multiple outputs via the OR array, effectively

increasing design density.

The XCR5064 CPLDs are supported by industry standard

CAE tools (Cadence/OrCAD, Exemplar Logic, Mentor,

Synopsys, Synario, Viewlogic, and Synplicity), using text

(ABEL, VHDL, Verilog) and/or schematic entry. Design ver-

ification uses industry standard simulators for functional

and timing simulation. Development is supported on per-

sonal computer, Sparc, and HP platforms. Device fitting

uses a Xilinx developed tool, XPLA Professional (available

on the Xilinx web site).

The XCR5064 CPLD is reprogrammable using industry

standard device programmers from vendors such as Data

I/O, BP Microsystems, SMS, and others.

Features.

•

Industry's first TotalCMOS™ PLD - both CMOS design

and process technologies

Fast Zero Power (FZP™) design technique provides

ultra-low power and very high speed

High speed pin-to-pin delays of 7.5 ns

Ultra-low static power of less than 100

100% routable with 100% utilization while all pins and

all macrocells are fixed

Deterministic timing model that is extremely simple to

use

Four clocks available

Programmable clock polarity at every macrocell

Support for asynchronous clocking

Innovative XPLA™ architecture combines high speed

with extreme flexibility

1000 erase/program cycles guaranteed

20 years data retention guaranteed

Logic expandable to 37 product terms

PCI compliant

Advanced 0.5

CMOS process

Security bit prevents unauthorized access

Design entry and verification using industry standard

and Xilinx CAE tools

Reprogrammable using industry standard device

programmers

Innovative Control Term structure provides either sum

terms or product terms in each logic block for:

- Programmable 3-state buffer

- Asynchronous macrocell register preset/reset

Programmable global 3-state pin facilitates `bed of

nails' testing without using logic resources

Available in PLCC,VQFP, and PQFP packages

Available in both Commercial and Industrial grades

•

Description

The XCR5064 CPLD (Complex Programmable Logic

Device) is the second in a family of CoolRunner

CPLDs

from Xilinx. These devices combine high speed and zero

power in a 64 macrocell CPLD. With the FZP design tech-

nique, the XCR5064 offers true pin-to-pin speeds of 7.5 ns,

while simultaneously delivering power that is less than 100

A at standby without the need for ‘ turbo bits’ or other

power down schemes. By replacing conventional sense

amplifier methods for implementing product terms (a tech-

nique that has been used in PLDs since the bipolar era)

with a cascaded chain of pure CMOS gates, the dynamic

power is also substantially lower than any competing

DS043 (v1.3) October 9, 2000

www.xilinx.com

1-800-255-7778

This product has been discontinued. Please see

www.xilinx.com/partinfo/notify/pdn0007.htm

for details.

XCR5064: 64 Macrocell CPLD

XPLA Architecture

Figure 1

shows a high level block diagram of a 64 macro-

cell device implementing the XPLA architecture. The

XPLA

architecture consists of logic blocks that are inter-

connected by a Zero-power Interconnect Array (ZIA). The

ZIA is a virtual crosspoint switch. Each logic block is essen-

tially a 36V16 device with 36 inputs from the ZIA and 16

macrocells. Each logic block also provides 32 ZIA feedback

paths from the macrocells and I/O pins.

From this point of view, this architecture looks like many

other CPLD architectures. What makes the CoolRunner

family unique is what is inside each logic block and the

design technique used to implement these logic blocks.

The contents of the logic block will be described next.

figured as either SUM or PRODUCT terms, and are used to

control the preset/reset and output enables of the 16 mac-

rocells’ flip-flops. The PAL array consists of a programma-

ble AND array with a fixed OR array, while the PLA array

consists of a programmable AND array with a programma-

ble OR array. The PAL array provides a high speed path

through the array, while the PLA array provides increased

product term density.

Each macrocell has five dedicated product terms from the

PAL array. The pin-to-pin t

of the XCR5064 device

through the PAL array is 7.5 ns. If a macrocell needs more

than five product terms, it simply gets the additional product

terms from the PLA array. The PLA array consists of 32

product terms, which are available for use by all 16 macro-

cells. The additional propagation delay incurred by a mac-

rocell using one or all 32 PLA product terms is just 2.0 ns.

So the total pin-to-pin t

for the XCR5064 using six to 37

product terms is 9.5 ns (7.5 ns for the PAL + 2.0 ns for the

PLA).

Logic Block Architecture

Figure 2

illustrates the logic block architecture. Each logic

block contains control terms, a PAL array, a PLA array, and

16 macrocells. the six control terms can individually be con-

MC1

MC2

I/O

MC16

ZIA

MC1

MC2

I/O

MC16

LOGIC

BLOCK

LOGIC

BLOCK

LOGIC

BLOCK

LOGIC

BLOCK

MC1

MC2

I/O

MC16

MC1

MC2

I/O

MC16

SP00439

Figure 1: Xilinx XPLA CPLD Architecture

DS043 (v1.3) October 9, 2000

www.xilinx.com

1-800-255-7778

This product has been discontinued. Please see

www.xilinx.com/partinfo/notify/pdn0007.htm

for details.

XCR5064: 64 Macrocell CPLD

36 ZIA INPUTS

CONTROL

PAL

ARRAY

PLA

ARRAY

(32)

SP00435A

Figure 2: Xilinx XPLA Logic Block Architecture

www.xilinx.com

1-800-255-7778

DS043 (v1.3) October 9, 2000

TO 16 MACROCELLS

This product has been discontinued. Please see

www.xilinx.com/partinfo/notify/pdn0007.htm

for details.

XCR5064: 64 Macrocell CPLD

Macrocell Architecture

Figure 3

shows the architecture of the macrocell used in

the CoolRunner family. The macrocell consists of a flip-flop

that can be configured as either a D- or T-type. A D-type

flip-flop is generally more useful for implementing state

machines and data buffering. A T-type flip-flop is generally

more useful in implementing counters. All CoolRunner fam-

ily members provide both synchronous and asynchronous

clocking and provide the ability to clock off either the falling

or rising edges of these clocks. These devices are

designed such that the skew between the rising and falling

edges of a clock are minimized for clocking integrity. There

are 4 clocks available on the XCR5064 device. Clock 0

(CLK0) is designated as the “synchronous” clock and must

be driven by an external source. Clock 1 (CLK1), Clock 2

(CLK2), and Clock 3 (CLK3) can either be used as a syn-

chronous clock (driven by an external source) or as an

asynchronous clock (driven by a macrocell equation). The

timing for asynchronous clocks is different in that the t

time is extended by the amount of time that it takes for the

signal to propagate through the array and reach the clock

network, and the t

time is reduced.

Two of the control terms (CT0 and CT1) are used to control

the Preset/Reset of the macrocell’s flip-flop. The Pre-

set/Reset feature for each macrocell can also be disabled.

Note that the Power-on Reset leaves all macrocells in the

“zero” state when power is properly applied. The other four

control terms (CT2-CT5) can be used to control the Output

Enable of the macrocell's output buffers. The reason there

are as many control terms dedicated for the Output Enable

of the macrocell is to insure that all CoolRunner devices are

PCI compliant. The macrocell's output buffers can also be

always enabled or disabled. All CoolRunner devices also

provide a Global 3-state (GTS) pin, which, when enabled

and pulled Low, will 3-state all the outputs of the device.

This pin is provided to support “In-Circuit Testing” or

“Bed-of-Nails Testing”.

There are two feedback paths to the ZIA: one from the

macrocell, and one from the I/O pin. The ZIA feedback path

before the output buffer is the macrocell feedback path,

while the ZIA feedback path after the output buffer is the I/O

pin ZIA path. When the macrocell is used as an output, the

output buffer is enabled, and the macrocell feedback path

can be used to feedback the logic implemented in the mac-

rocell. When the I/O pin is used as an input, the output

buffer will be 3-stated and the input signal will be fed into

the ZIA via the I/O feedback path, and the logic imple-

mented in the buried macrocell can be fed back to the ZIA

via the macrocell feedback path. It should be noted that

unused inputs or I/Os should be properly terminated.

Terminations

The CoolRunner XCR5064 CPLDs are TotalCMOS

devices. As with other CMOS devices, it is important to

consider how to properly terminate unused inputs and I/O

pins when fabricating a PC board. Allowing unused inputs

and I/O pins to float can cause the voltage to be in the lin-

ear region of the CMOS input structures, which can

increase the power consumption of the device. The

XCR5064 CPLDs have programmable on-chip pull-down

resistors on each I/O pin. These pull-downs are automati-

cally activated by the fitter software for all unused I/O pins.

Note that an I/O macrocell used as buried logic that does

not have the I/O pin used for input is considered to be

unused, and the pull-down resistors will be turned on. We

recommend that any unused I/O pins on the XCR5064

device be left unconnected.

There are no on-chip pull-down structures associated with

the dedicated input pins. Xilinx recommends that any

unused dedicated inputs be terminated with external 10k

Ω

pull-up resistors. These pins can be directly connected to

or GND, but using the external pull-up resistors main-

tains maximum design flexibility should one of the unused

dedicated inputs be needed due to future design changes.

DS043 (v1.3) October 9, 2000

www.xilinx.com

1-800-255-7778

This product has been discontinued. Please see

www.xilinx.com/partinfo/notify/pdn0007.htm

for details.

XCR5064: 64 Macrocell CPLD

TO ZIA

PAL

PLA

D/T

INIT

(P or R)

CLK0

CLK1

CLK2

CLK3

CT0

CT1

GND

CT2

CT3

CT4

CT5

GND

SP00457

GTS

GND

Figure 3: XCR5064 Macrocell Architecture

Simple Timing Model

Figure 4

shows the CoolRunner Timing Model. The Cool-

Runner timing model looks very much like a 22V10 timing

model in that there are three main timing parameters,

including t

, t

, and t

. In other architectures, the user

may be able to fit the design into the CPLD, but is not sure

whether system timing requirements can be met until after

the design has been fit into the device. This is because the

timing models of competing architectures are very complex

and include such things as timing dependencies on the

number of parallel expanders borrowed, sharable expand-

ers, varying number of X and Y routing channels used, etc.

In the XPLA architecture, the user knows up front whether

the design will meet system timing requirements. This is

due to the simplicity of the timing model. For example, in

the XCR5064 device, the user knows up front that if a given

output uses 5product terms or less, the t

= 7.5 ns, the

SU_PAL

= 4 ns, and the t

= 5.5 ns. If an output is using six

to 37 product terms, an additional 2 ns must be added to

the t

and t

timing parameters to account for the time to

propagate through the PLA array.

TotalCMOS Design Technique for Fast Zero

Power

Xilinx is the first to offer a TotalCMOS CPLD, both in pro-

cess technology and design technique. Xilinx employs a

cascade of CMOS gates to implement its Sum of Products

instead of the traditional sense amp approach. This CMOS

gate implementation allows Xilinx to offer CPLD which are

both high performance and low power, breaking the para-

digm that to have low power, you must have low perfor-

mance. Refer to

Figure 5

and

Table 1

showing the I

vs.

Frequency of our XCR5064 TotalCMOS CPLD.

INPUT PIN

PD_PAL

= COMBINATORIAL PAL ONLY

PD_PLA

= COMBINATORIAL PAL + PLA

OUTPUT PIN

INPUT PIN

REGISTERED

SU_PAL

= PAL ONLY

SU_PLA

= PAL + PLA

REGISTERED

OUTPUT PIN

GLOBAL CLOCK PIN

SP00441

Figure 4: CoolRunner Timing Model

www.xilinx.com

1-800-255-7778

DS043 (v1.3) October 9, 2000

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