VSC7125QN datasheet, PDF - EEWORLD Datasheet

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VSC7125QN: Description1.0625 Gbits/sec Fibre Channel Transceiver; CategoryWireless rf/communication Telecom circuit; File Size89KB，16 Pages; ManufacturerVitesse Semiconductor Corporation; Websitehttp://www.vitesse.com/

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VSC7125QN Overview

1.0625 Gbits/sec Fibre Channel Transceiver

VSC7125QN Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Vitesse Semiconductor Corporation
Parts packaging code	QFP
package instruction	QFP, QFP64,.66SQ,32
Contacts	64
Reach Compliance Code	unknow
JESD-30 code	S-PQFP-G64
JESD-609 code	e0
length	14 mm
Number of functions	1
Number of terminals	64
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	QFP
Encapsulate equivalent code	QFP64,.66SQ,32
Package shape	SQUARE
Package form	FLATPACK
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Certification status	Not Qualified
Maximum seat height	2.35 mm
Maximum slew rate	0.26 mA
Nominal supply voltage	3.3 V
surface mount	YES
technology	GAAS
Telecom integrated circuit types	TELECOM CIRCUIT
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	0.8 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED
width	14 mm

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VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC7125

Features

• ANSI X3T11 Fibre Channel Compatible

1.0625 Gbps Full-duplex Transceiver

• 10 Bit TTL Interface for Transmit and

Receive Data

• Monolithic Clock Synthesis and Clock

Recovery - No External Components

1.0625 Gbits/sec Fibre

Channel Transceiver

• 106.25 MHz TTL Reference Clock

• Low Power Operation - 650 mW

• Suitable for Both Coaxial and Optical

Link Applications

• 64 Pin, 10mm or 14mm PQFP

• Single +3.3V Power Supply

General Description

The VSC7125 is a full-speed Fibre Channel Transceiver optimized for Disk Drive and other space con-

strained applications. It accepts 10-bit 8B/10B encoded transmit data, latches it on the rising edge of REFCLK

and serializes it onto the TX PECL differential outputs at a baud rate which is ten times the REFCLK frequency.

The VSC7125 also samples serial receive data on the RX PECL differential inputs, recovers the clock and data,

deserializes it onto the 10-bit receive data bus, outputs two recovered clocks at one twentieth of the incoming

baud rate and detects Fibre Channel “Comma” characters. The VSC7125 contains on-chip PLL circuitry for

synthesis of the baud-rate transmit clock, and extraction of the clock from the received serial stream. These cir-

cuits are fully monolithic and require no external components.

VSC7125 Block Diagram

EWRAP

R0:9

Serial to

Parallel

Retimed

Data

Recovered

Clock

Recovery

2:1

RX+

RX-

RCLK

RCLKN

Frame

Logic

Comma

Detect

Resync

COM_DET

EN_CDET

T0:9

Parallel

to Serial

Serial Data

Synthesized

Clock

TX+

TX-

REFCLK

PLL Clock

Multiply

G52121-0, Rev. 4.1

4/23/98

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page 1

VITESSE

SEMICONDUCTOR CORPORATION

1.0625 Gbits/sec Fibre

Channel Transceiver

Data Sheet

VSC7125

Functional Description

Clock Synthesizer

The VSC7125 clock synthesizer multiplies the reference frequency provided on the REFCLK pin by 10 to

achieve a baud rate clock at nominally 1.0625 GHz. The clock synthesizer contains a fully monolithic PLL

which does not require any external components.

Serializer

The VSC7125 accepts TTL input data as a parallel 10 bit character on the T0:9 bus which is latched into the

input latch on the rising edge of REFCLK. This data will be serialized and transmitted on the TX PECL differ-

ential outputs at a baud rate of ten times the frequency of the REFCLK input, with bit T0 transmitted ﬁrst. User

data should be encoded for transmission using the 8B/10B block code described in the Fibre Channel speciﬁca-

tion, or an equivalent, edge rich, DC-balanced code.

Transmission Character Interface

In Fibre Channel, an encoded byte is 10 bits and is referred to as a transmission character. The 10 bit inter-

face on the VSC7125 corresponds to a transmission character. This mapping is illustrated below.

Figure 1: Transmission Order and Mapping to Fibre Channel Character

Parallel Data Bits

8B/10B Bit Position

Comma Character

Last Data Bit Transmitted

Clock Recovery

First Data Bit Transmitted

The VSC7125 accepts differential high speed serial inputs on the RX+/RX- pins, extracts the clock and

retimes the data. The serial bit stream should be encoded to provide DC balance and limited run length by a

Fibre Channel compatible 8B/10B transmitter or equivalent. The VSC7125 clock recovery circuitry is com-

pletely monolithic and requires no external components. For proper operation, the baud rate of the data stream

to be recovered should be within 0.01% of ten times the REFCLK frequency. For example if the REFCLK used

is 106.25MHz, then the incoming serial baud rate must be 1.0625 gigabaud +0.01%.

Deserializer

The retimed serial bit stream is converted into a 10-bit parallel output character. The VSC7125 provides

complementary TTL recovered clocks, RCLK and RCLKN, which are at one twentieth of the serial baud rate.

This architecture is designed to simplify demultiplexing of the 10-bit data characters into a 20-bit halfword in

the downstream controller chip. The clocks are generated by dividing down the high-speed clock which is phase

locked to the serial data. The serial data is retimed by the internal high-speed clock, and deserialized. The

Page 2

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

G52121-0, Rev. 4.1

4/23/98

VITESSE

SEMICONDUCTOR CORPORATION

Data Sheet

VSC7125

1.0625 Gbits/sec Fibre

Channel Transceiver

resulting parallel data will be captured by the adjoining protocol logic on the rising edges of RCLK and

RCLKN. In order to maximize the setup and hold times available at this interface, the parallel data is loaded

into the output register at a point nominally midway between the transition edges of RCLK and RCLKN.

If serial input data is not present, or does not meet the required baud rate, the VSC7125 will continue to

produce a recovered clock so that downstream logic may continue to function. The RCLK and RCLKN output

frequency under these circumstances may differ from their expected frequency by no more than +1%.

Word Alignment

The VSC7125 provides 7-bit Fibre Channel comma character recognition and data word alignment. Word

synchronization is enabled by asserting EN_CDET HIGH. When synchronization is enabled, the VSC7125 con-

stantly examines the serial data for the presence of the Fibre Channel “comma” character. This pattern is

“0011111XXX”, where the leading zero corresponds to the ﬁrst bit received. The comma sequence is not con-

tained in any normal 8B/10B coded data character or pair of adjacent characters. It occurs only within special

characters, known as K28.1, K28.5 and K28.7, which is deﬁned speciﬁcally for synchronization in Fibre Chan-

nel systems. Improper alignment of the comma character is deﬁned as any of the following conditions:

1) The comma is not aligned within the 10-bit transmission character such that T0...T6 = “0011111”

2) The comma straddles the boundary between two 10-bit transmission characters.

3) The comma is properly aligned but occurs in the received character presented during the rising edge of

RCLK rather than RCLKN.

When EN_CDET is HIGH and an improperly aligned comma is encountered, the internal data is shifted in

such a manner that the comma character is aligned properly in R0:9. This results in proper character and half-

word alignment. When the parallel data alignment changes in response to an improperly aligned comma pattern,

some data which would have been presented on the parallel output port may be lost. However, the synchroniza-

tion character and subsequent data will be output correctly and properly aligned. When EN_CDET is LOW, the

current alignment of the serial data is maintained indeﬁnitely, regardless of data pattern.

On encountering a comma character, COM_DET is driven HIGH to inform the user that realignment of the

parallel data ﬁeld may have occurred. The COM_DET pulse is presented simultaneously with the comma char-

acter and has a duration equal to the data, or half of an RCLK period. The COM_DET signal is timed such that

it can be captured by the adjoining protocol logic on the rising edge of RCLKN. Functional waveforms for syn-

chronization are given in Figure 2 and Figure 3. Figure 2 shows the case when a comma character is detected

and no phase adjustment is necessary. It illustrates the position of the COM_DET pulse in relation to the comma

character on R0:9. Figure 3 shows the case where the K28.5 is detected, but it is out of phase and a change in

the output data alignment is required. Note that up to three characters prior to the comma character may be cor-

rupted by the realignment process.

G52121-0, Rev. 4.1

4/23/98

VITESSE

SEMICONDUCTOR CORPORATION

741 Calle Plano, Camarillo, CA 93012 • 805/388-3700 • FAX: 805/987-5896

Page 3

VSC7125QN Related Products

	VSC7125QN	VSC7125QU	VSC7125
Description	1.0625 Gbits/sec Fibre Channel Transceiver	1.0625 Gbits/sec Fibre Channel Transceiver	1.0625 Gbits/sec Fibre Channel Transceiver
Is it Rohs certified?	incompatible	incompatible	-
Maker	Vitesse Semiconductor Corporation	Vitesse Semiconductor Corporation	-
Parts packaging code	QFP	QFP	-
package instruction	QFP, QFP64,.66SQ,32	FQFP, QFP64,.51SQ,20	-
Contacts	64	64	-
Reach Compliance Code	unknow	unknow	-
JESD-30 code	S-PQFP-G64	S-PQFP-G64	-
JESD-609 code	e0	e0	-
length	14 mm	10 mm	-
Number of functions	1	1	-
Number of terminals	64	64	-
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	-
encapsulated code	QFP	FQFP	-
Encapsulate equivalent code	QFP64,.66SQ,32	QFP64,.51SQ,20	-
Package shape	SQUARE	SQUARE	-
Package form	FLATPACK	FLATPACK, FINE PITCH	-
Peak Reflow Temperature (Celsius)	NOT SPECIFIED	NOT SPECIFIED	-
power supply	3.3 V	3.3 V	-
Certification status	Not Qualified	Not Qualified	-
Maximum seat height	2.35 mm	2.45 mm	-
Maximum slew rate	0.26 mA	0.26 mA	-
Nominal supply voltage	3.3 V	3.3 V	-
surface mount	YES	YES	-
technology	GAAS	GAAS	-
Telecom integrated circuit types	TELECOM CIRCUIT	TELECOM CIRCUIT	-
Terminal surface	Tin/Lead (Sn/Pb)	Tin/Lead (Sn/Pb)	-
Terminal form	GULL WING	GULL WING	-
Terminal pitch	0.8 mm	0.5 mm	-
Terminal location	QUAD	QUAD	-
Maximum time at peak reflow temperature	NOT SPECIFIED	NOT SPECIFIED	-
width	14 mm	10 mm	-

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