8Mx72 bit SDRAM “Intel” Registered DIMM H-Series
without PLL & PC/100 SDRAM Specification Supporting
based on 8Mx8 SDRAM, LVTTL, 2/4-Banks & 4K/8KRefresh
HYM7V75AE800A/ HYM7V75AE801A/ HYM7V75AE830A/ HYM7V75AE831A
DESCRIPTION
The HYM7V75AE800A/ 75AE801A/ 75AE830A/ 75AE831A H-Series are high speed 3.3-Volt synchro-
nous dynamic RAM Modules composed of nine 8Mx8 bit Synchronous DRAMs in 54-pin TSOPII, two 48-pin
SOP Register Buffers and 8-pin TSSOP 2K bit E
2
PROM on a 168-pin glass-epoxy printed circuit board. A
0.22µF and 0.0022µF decoupling capacitors per each SDRAM are mounted on the module.
The HYM7V75AE800A/ 75AE801A/ 75AE830A/ 75AE831A H-Series are gold plated socket type Dual In-
line Memory Modules suitable for easy interchange and addition of 64M bytes memory. All addresses, data
and control inputs are latched on the rising edge of the master clock input. The data paths are internally
pipelined to achieve very high bandwidths.
FEATURES
•
•
•
•
•
•
•
•
•
•
•
•
1.500” (38.10mm) PCB Height
168-Pin Registered DIMM with Double Sided
ECC support
One 0.22µF and one 0.0022µF decoupling
capacitors adopted
Serial Presence Detect with Serial E
2
PROM
Two Register Buffers & one Inverter used
(without PLL)
Supports Flow-through or Register mode by Pin
No. 147 (REGE)
Meets all the other JEDEC specifications
Single 3.3V±0.3V power supply
All device pins are LVTTL compatible
4096 refresh cycles every 64ms or 8192 refresh
cycles every 128ms
Auto precharge/precharge all banks by A
10
flag
•
Possible to assert random column address
every clock cycle
•
Interleaved auto refresh mode
•
Programmable burst lengths and sequences
- 1,2,4,8,full page for Sequential type
- 1,2,4,8 for Interleave type
•
Programmable /CAS latency ; 2,3 clocks
•
Support clock suspend/power down mode by
CKE0
•
Data mask function by DQM
•
Mode register set programming
•
Burst termination command
•
Self refresh provides minimum power, full
internal refresh control
ORDERING INFORMATION
Part No.
HYM7V75AE800ATHG - 8/10P/10S
HYM7V75AE801ATHG - 8/10P/10S
HYM7V75AE830ATHG - 8/10P/10S
HYM7V75AE831ATHG - 8/10P/10S
Max. Frequency
125/ 100/ 100 MHz
125/ 100/ 100 MHz
125/ 100/ 100 MHz
125/ 100/ 100 MHz
SDRAM Bank
2 Banks
4 Banks
2 Banks
4 Banks
Ref.
4K
4K
8K
8K
Package
TSOPII
TSOPII
TSOPII
TSOPII
Plating
Gold
Gold
Gold
Gold
BASED COMPONENTS
Module Part No.
HYM7V75AE800ATHG
HYM7V75AE801ATHG
Based Comp. Part No.
Module Part No.
HY57V658010ATC
HYM7V75AE830ATHG
HY57V658020ATC
HYM7V75AE831ATHG
Based Comp. Part No.
HY57V648010ATC
HY57V648020ATC
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume
any responsibility for use of circuits described. No patent licenses are implied.
Sep. 1998
Rev 4.0
HYM7V75AE800A/ HYM7V75AE801A/ HYM7V75AE830A/ HYM7V75AE831A H-Series
PIN DESCRIPTION
Pin Name
CK0-CK3
Pin Type
INPUT
Description
System Clock Input; All other inputs except CKE are registered
to the SDRAM on the rising edge of CLK.
Clock Enable; Controls internal clock signal and when deactiva-
ted, the SDRAM will be either one of the states among power
down, suspend, or self refresh.
Chip select; Functions command mask(NOP).
Row address strobe
Column address strobe
Write Enable
Data Input / Output Mask
Data Input / Output; Include inputs, outputs, or Hi-z state.
Check Bit Input / Output; Include inputs, outputs, or Hi-z state.
Power Supplies; 3.3V±0.3V
Ground
Serial Address and Data Input / Output.
Serial Clock
Addresses in Serial E
2
PROM for Socket Presence.
CKE0
/S0, /S2
/RAS
/CAS
/WE
DQM0-7
DQ0-DQ63
CB0-CB7
V
CC
V
SS
SDA
SCL
SA0-SA2
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT/
OUTPUT
INPUT/
OUTPUT
SUPPLY
SUPPLY
INPUT/
OUTPUT
INPUT
INPUT
HYM7V75AE800A/HYM7V75AE830A H-Series ( 2Bank 8Mx8 SDRAM Based )
Pin Name
BA0
Pin Type
INPUT
Description
Bank select address inputs; Select one of dual banks during
both /RAS and /CAS activity.
Address Inputs;
A0-A8; X&Y addresses
A10; Precharge flag, A9-A12; X addresses only.
A0-A12
INPUT
HYM7V75AE801A/HYM7V75AE831A H-Series ( 4Bank 8Mx8 SDRAM Based )
Pin Name
BA0, BA1
Pin Type
INPUT
Description
Bank address inputs; Select one of quad banks during both
/RAS and /CAS activity.
Address Inputs;
A0-A8; X&Y addresses
A10; Precharge flag, A9-A11; X addresses only.
A0-A11
INPUT
Rev 4.0
2
HYM7V75AE800A/ HYM7V75AE801A/ HYM7V75AE830A/ HYM7V75AE831A H-Series
PIN NAME
#
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
NAME
Vss
DQ0
DQ1
DQ2
DQ3
Vcc
DQ4
DQ5
DQ6
DQ7
DQ8
Vss
DQ9
DQ10
DQ11
DQ12
DQ13
Vcc
DQ14
DQ15
CB0
CB1
Vss
NC
NC
Vcc
/WE
DQM0
DQM1
/S0
NC
Vss
A0
A2
A4
A6
A8
A10(AP)
* BA1
Vcc
Vcc
CK0
#
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
NAME
Vss
NC
/S2
DQM2
DQM3
NC
Vcc
NC
NC
CB2
CB3
Vss
DQ16
DQ17
DQ18
DQ19
Vcc
DQ20
NC
NC
NC
Vss
DQ21
DQ22
DQ23
Vss
DQ24
DQ25
DQ26
DQ27
Vcc
DQ28
DQ29
DQ30
DQ31
Vss
CK2
NC
WP
SDA
SCL
Vcc
#
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
NAME
Vss
DQ32
DQ33
DQ34
DQ35
Vcc
DQ36
DQ37
DQ38
DQ39
DQ40
Vss
DQ41
DQ42
DQ43
DQ44
DQ45
Vcc
DQ46
DQ47
CB4
CB5
Vss
NC
NC
Vcc
/CAS
DQM4
DQM5
NC
/RAS
Vss
A1
A3
A5
A7
A9
BA0
A11
Vcc
CK1
* A12
#
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
NAME
Vss
CKE0
NC
DQM6
DQM7
NC
Vcc
NC
NC
CB6
CB7
Vss
DQ48
DQ49
DQ50
DQ51
Vcc
DQ52
NC
NC
REGE
Vss
DQ53
DQ54
DQ55
Vss
DQ56
DQ57
DQ58
DQ59
Vcc
DQ60
DQ61
DQ62
DQ63
Vss
CK3
NC
SA0
SA1
SA2
Vcc
Note : 1. BA1 is used for HYM7V75AE801A/ HYM7V75AE831A H-Series ( 4 Bank 8Mx8 Based )
2. A12 is used for HYM7V75AE800A/ HYM7V75AE830A H-Series ( 2 Bank 8Mx8 Based )
3
Rev 4.0
HYM7V75AE800A/ HYM7V75AE801A/ HYM7V75AE830A/ HYM7V75AE831A H-Series
BLOCK DIAGRAM
Note : 1. The serial resistor values of DQs are 10 Ohms.
Rev 4.0
4
HYM7V75AE800A/ HYM7V75AE801A/ HYM7V75AE830A/ HYM7V75AE831A H-Series
I-
1
SERIAL PRESENCE DETECT
BYTE
NUMBER
FUNCTION
DESCRIBED
[ HYM7V75AE800A/HYM7V75AE830A H-Series; 2 Banks ]
-8
FUNCTION
-10P
-10S
-8
VALUE
-10P -10S
NOTE
BYTE0
BYTE1
BYTE2
BYTE3
BYTE4
BYTE5
BYTE6
BYTE7
BYTE8
BYTE9
BYTE10
BYTE11
BYTE12
BYTE13
BYTE14
BYTE15
BYTE16
BYTE17
BYTE18
BYTE19
BYTE20
BYTE21
BYTE22
BYTE23
BYTE24
BYTE25
BYTE26
BYTE27
BYTE28
BYTE29
BYTE30
BYTE31
BYTE32
BYTE33
BYTE34
BYTE35
# of Bytes Written into Serial Memory
at Module Manufacturer
Total # of Bytes of SPD Memory Device
Fundamental Memory Type
# of Row Addresses on This Assembly
# of Column Addresses on This Assembly
# of Module Banks on This Assembly
Data Width of This Assembly
Data Width of This Assembly (Continued)
Voltage Interface Standard of This Assembly
SDRAM Cycle Time
@
/CAS Latency=3
Access Time from Clock
@
/CAS Latency=3
DIMM Configuration Type
Refresh Rate/Type
Primary SDRAM Width
Error Checking SDRAM Width
Minimum Clock Delay Back to Back Random
Column Address
Burst Lengths Supported
# of Banks on SDRAM Device
SDRAM Device Attributes, CAS # Latency
SDRAM Device Attributes, CS # Latency
SDRAM Device Attributes, Write Latency
SDRAM Module Attributes
SDRAM Device Attributes, General
SDRAM Cycle Time
@
/CAS Latency=2
Access Time from Clock @ /CAS Latency=2
SDRAM Cycle Time @ /CAS Latency=1
Access Time from Clock @ /CAS Latency=1
Minimum Row Precharge Time (t
RP
)
Minimum Row Active to Row Active Delay (t
RRD
)
Minimum /RAS to /CAS Delay (t
RCD
)
Minimum /RAS Pulse width (t
RAS
)
Module Bank Density
Command & Address signal input setup time (t
AS
)
Command & Address signal input hold time (t
AH
)
Data signal input setup time (t
DS
)
Data signal input hold time (t
DH
)
8ns
6ns
128 Bytes
256 Bytes
SDRAM
2 Banks; 13
9
1 Bank
72 Bits
-
LVTTL
10ns
6ns
ECC
15.625µs
/ Self Refresh Supported
80h
08h
04h
0Dh
09h
01h
48h
00h
01h
10ns
6ns
80h
60h
A0h
60h
02h
80h
08h
08h
01h
8Fh
02h
06h
01h
01h
12h
06h
A0h
60h
00h
00h
14h
10h
14h
30h
20h
10h
20h
10h
A0h
60h
00h
00h
14h
14h
14h
32h
10h
20h
10h
20h
10h
C0h
60h
00h
00h
14h
14h
14h
32h
20h
10h
20h
10h
2
A0h
60h
1
x8
x8
t
CCD
=1 Latency
1,2,4,8,Full Page
2 Banks
/CAS Latency=2,3
/CS Latency=0
/WE Latency=0
Registered w/o PLL
+/-10% voltage
tolerance, Burst read,
Precharge all, Auto
prechare
10ns 10ns 12ns
6ns
6ns
6ns
-
-
-
-
-
-
20ns 20ns 20ns
16ns 20ns 20ns
20ns 20ns 20ns
48ns 50ns 50ns
64MB
2ns
2ns
2ns
1ns
1ns
1ns
2ns
2ns
2ns
1ns
1ns
1ns
5
Rev 4.0
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