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Datasheet> All Categories > Analog mixed-signal IC> converter> LTC2351CUH-12#TR
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LTC2351CUH-12#TR

Description
IC 6-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC32, 5 X 5 MM, PLASTIC, MO-220WHHD, QFN-32, Analog to Digital Converter
CategoryAnalog mixed-signal IC    converter   
File Size274KB，20 Pages
ManufacturerLinear ( ADI )
Websitehttp://www.analog.com/cn/index.html
Download Datasheet Parametric Compare View All

LTC2351CUH-12#TR Overview

IC 6-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC32, 5 X 5 MM, PLASTIC, MO-220WHHD, QFN-32, Analog to Digital Converter

LTC2351CUH-12#TR Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerLinear ( ADI )
Parts packaging codeQFN
package instructionHVQCCN, LCC32,.2SQ,20
Contacts32
Reach Compliance Codenot_compliant
ECCN codeEAR99
Maximum analog input voltage2.5 V
Converter typeADC, PROPRIETARY METHOD
JESD-30 codeS-PQCC-N32
JESD-609 codee0
length5 mm
Maximum linear error (EL)0.0244%
Humidity sensitivity level1
Number of analog input channels6
Number of digits12
Number of functions1
Number of terminals32
Maximum operating temperature70 °C
Minimum operating temperature
Output bit codeOFFSET BINARY, 2\'S COMPLEMENT BINARY
Output formatSERIAL
Package body materialPLASTIC/EPOXY
encapsulated codeHVQCCN
Encapsulate equivalent codeLCC32,.2SQ,20
Package shapeSQUARE
Package formCHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)235
power supply3 V
Certification statusNot Qualified
Sampling rate1.5 MHz
Sample and hold/Track and holdSAMPLE
Maximum seat height0.8 mm
Nominal supply voltage3 V
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formNO LEAD
Terminal pitch0.5 mm
Terminal locationQUAD
Maximum time at peak reflow temperature20
width5 mm

LTC2351CUH-12#TR Preview

LTC2351-12
6 Channel, 12-Bit, 1.5Msps
Simultaneous Sampling ADC
with Shutdown
DESCRIPTIO
The LTC
®
2351-12 is a 12-bit, 1.5Msps ADC with six
simultaneously sampled differential inputs. The device
draws only 5.5mA from a single 3V supply, and comes in
a tiny 32-pin (5mm
×
5mm) QFN package. A SLEEP
shutdown mode further reduces power consumption to
12µW. The combination of low power and tiny package
makes the LTC2351-12 suitable for portable applications.
The LTC2351-12 contains six separate differential inputs
that are sampled simultaneously on the rising edge of the
CONV signal. These six sampled inputs are then
converted at a rate of 250ksps per channel.
The 83dB common mode rejection allows users to
eliminate ground loops and common mode noise by
measuring signals differentially from the source.
The device converts 0V to 2.5V unipolar inputs differen-
tially, or
±1.25V
bipolar inputs also differentially,
depending on the state of the BIP pin. Any analog input
may swing rail-to-rail as long as the differential input
range is maintained.
The conversion sequence can be abbreviated to convert
fewer than six channels, depending on the logic state of
the SEL2, SEL1 and SEL0 inputs.
The serial interface sends out the six conversion results in
96 clocks for compatibility with standard serial interfaces.
FEATURES
■
■
■
■
■
■
■
■
■
■
■
■
■
1.5Msps ADC with 6 Simultaneously Sampled
Differential Inputs
250ksps Throughput per Channel
72dB SINAD
Low Power Dissipation: 16.5mW
3V Single Supply Operation
2.5V Internal Bandgap Reference, Can be Overdriven
with External Reference
3-Wire SPI-Compatible Serial Interface
Internal Conversion Triggered by CONV
SLEEP (12µW) Shutdown Mode
NAP (4.5mW) Shutdown Mode
0V to 2.5V Unipolar, or
±1.25V
Bipolar Differential
Input Range
83dB Common Mode Rejection
Tiny 32-Pin (5mm
×
5mm) QFN Package
APPLICATIO S
■
■
■
■
Multiphase Power Measurement
Multiphase Motor Control
Data Acquisition Systems
Uninterruptable Power Supplies
, LT, LTC and LTM are registered trademarks of Linear Technology Corporation.
All other trademarks are the property of their respective owners.
Protected by U.S. Patents including 6084440, 6522187.
BLOCK DIAGRA
CH5
–
21
CH5
+
20
19
CH4
–
18
CH4
+
17
10µF
CH3
–
15
CH3
+
14
12
13
CH2
–
11
CH2
+
10
9
CH1
–
8
CH1
+
7
6
5
CH0
–
4
CH0
+
24
V
CC
16
–
–
S AND H
–
–
–
–
S AND H
S AND H
S AND H
S AND H
S AND H
1.5Msps
12-BIT ADC
MUX
TIMING
LOGIC
30
32
31
33
22
GND
10µF
23
V
REF
29
BIP
26
27
28
235112 TA01
2.5V
REFERENCE
U
W
U
3V
V
DD
25
12-BIT LATCH 0
12-BIT LATCH 1
12-BIT LATCH 2
12-BIT LATCH 3
12-BIT LATCH 4
12-BIT LATCH 5
OV
DD
3V
SD0
OGND
0.1µF
+
+
+
+
+
+
THREE-
STATE
SERIAL
OUTPUT
PORT
3
1
2
CONV
SCK
DGND
SEL2 SEL1 SEL0
235112f
1
LTC2351-12
ABSOLUTE
(Notes 1, 2)
AXI U
RATI GS
PACKAGE/ORDER I FOR ATIO
TOP VIEW
16 15 14 13 12 11 10 9
CH4
+
17
CH4
–
18
GND 19
CH5
+
20
CH5
–
Supply Voltage (V
DD
, V
CC
, OV
DD
) .............................. 4V
Analog and V
REF
Input Voltages
(Note 3) ................................... – 0.3V to (V
DD
+ 0.3V)
Digital Input Voltages .................. – 0.3V to (V
DD
+ 0.3V)
Digital Output Voltage .................. – 0.3V to (V
DD
+ 0.3V)
Power Dissipation .............................................. 100mW
Operation Temperature Range
LTC2351C-12 .......................................... 0°C to 70°C
LTC2351I-12 ...................................... – 40°C to 85°C
Storage Temperature Range ................. – 65°C to 125°C
ORDER PART
NUMBER
8
7
6
CH1
–
CH1
+
GND
CH0
–
CH0
+
OV
DD
OGND
SDO
CH3
–
CH3
+
CH2
–
CH2
+
GND
GND
GND
GND
LTC2351CUH-12
LTC2351IUH-12
21
33
5
4
3
2
1
GND 22
V
REF
23
V
CC
24
25 26 27 28 29 30 31 32
QFN PART
MARKING
235112
V
DD
BIP
SEL2
SEL1
SEL0
CONV
QFN PACKAGE
32-PIN (5mm
×
5mm) PLASTIC QFN
T
JMAX
= 125°C,
θ
JA
= 34°C/ W
EXPOSED PIN IS GND (PAD 33)
MUST BE SOLDERED TO PCB
Order Options
Tape and Reel: Add #TR
Lead Free: Add #PBF Lead Free Tape and Reel: Add #TRPBF
Lead Free Part Marking:
http://www.linear.com/leadfree/
Consult LTC Marketing for parts specified with wider operating temperature ranges.
CO VERTER CHARACTERISTICS
PARAMETER
Resolution (No Missing Codes)
Integral Linearity Error
Offset Error
Offset Match from CH0 to CH5
Range Error
Range Match from CH0 to CH5
Range Tempco
The
●
denotes the specifications which apply over the full operating
temperature range, otherwise specifications are at T
A
= 25°C. With internal reference, V
DD
= V
CC
= 3V.
CONDITIONS
●
DGND
SCK
MIN
12
–1
–4.5
–3
–12
–5
●
●
●
TYP
±0.25
±1
±0.5
±2
±1
±15
±1
MAX
1
4.5
3
12
5
UNITS
Bits
LSB
mV
mV
mV
mV
ppm/°C
ppm/°C
(Note 5)
(Note 4)
(Note 4)
Internal Reference (Note 4)
External Reference
A ALOG I PUT
SYMBOL PARAMETER
V
IN
V
CM
I
IN
C
IN
t
ACQ
t
AP
t
JITTER
t
SK
CMRR
The
●
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. With internal reference, V
DD
= V
CC
= 3V.
CONDITIONS
2.7V
≤
V
DD
≤
3.6V, Unipolar
2.7V
≤
V
DD
≤
3.6V, Bipolar
(Note 8)
●
MIN
TYP
0 to 2.5
±1.25
0 to V
DD
MAX
UNITS
V
V
V
Analog Differential Input Range (Notes 3, 8, 9)
Analog Common Mode + Differential
Input Range
Analog Input Leakage Current
Analog Input Capacitance
Sample-and-Hold Acquisition Time
Sample-and-Hold Aperture Delay Time
Sample-and-Hold Aperture Delay Time Jitter
Channel to Channel Aperture Skew
Analog Input Common Mode Rejection Ratio
1
13
39
1
0.3
200
(Note 6)
●
f
IN
= 100kHz, V
IN
= 0V to 3V
f
IN
= 10MHz, V
IN
= 0V to 3V
–83
–67
235112f
2
U
µA
pF
ns
ns
ps
ps
dB
dB
W
U
U
W W
W
U
U
U
LTC2351-12
DY A IC ACCURACY
SYMBOL
SINAD
THD
SFDR
IMD
PARAMETER
Signal-to-Noise Plus
Distortion Ratio
Total Harmonic
Distortion
Spurious Free
Dynamic Range
Intermodulation
Distortion
Code-to-Code
Transition Noise
Full Power Bandwidth
Full Linear Bandwidth
The
●
denotes the specifications which apply over the full operating temperature range,
otherwise specifications are at T
A
= 25°C. With internal reference, V
DD
= V
CC
= 3V.
CONDITIONS
100kHz Input Signal
300kHz Input Signal
100kHz First 5 Harmonics
300kHz First 5 Harmonics
100kHz Input Signal
300kHz Input Signal
0.625V
P-P
, 833kHz into CH0+, 0.625V
P-P
, 841kHz into CH0–
Bipolar Mode. Also Applicable to Other Channels
V
REF
= 2.5V (Note 17)
V
IN
= 2.5V
P-P
, SDO = 11585LSB
P-P
(–3dBFS) (Note 15)
S/(N + D)
≥
68dB, Bipolar Differential Input
●
●
I TER AL REFERE CE CHARACTERISTICS
PARAMETER
V
REF
Output Voltage
V
REF
Output Tempco
V
REF
Line Regulation
V
REF
Output Resistance
V
REF
Settling Time
External V
REF
Input Range
CONDITIONS
I
OUT
= 0
DIGITAL I PUTS A D DIGITAL OUTPUTS
SYMBOL
V
IH
V
IL
I
IN
C
IN
V
OH
V
OL
I
OZ
C
OZ
I
SOURCE
I
SINK
PARAMETER
High Level Input Voltage
Low Level Input Voltage
Digital Input Current
Digital Input Capacitance
High Level Output Voltage
Low Level Output Voltage
Hi-Z Output Leakage D
OUT
Hi-Z Output Capacitance D
OUT
Output Short-Circuit Source Current
Output Short-Circuit Sink Current
V
OUT
= 0V, V
DD
= 3V
V
OUT
= V
DD
= 3V
CONDITIONS
V
DD
= 3.3V
V
DD
= 2.7V
V
IN
= 0V to V
DD
The
●
denotes the specifications which apply over the
full operating temperature range, otherwise specifications are at T
A
= 25°C. V
DD
= V
CC
= 3V.
MIN
●
●
●
U
U
U
W U
U
MIN
69
–80
TYP
72
71
–90
–85
90
85
–80
0.2
50
5
MAX
UNITS
dB
dB
dB
dB
dB
dB
dB
LSB
RMS
MHz
MHz
U
T
A
= 25°C. V
DD
= V
CC
= 3V.
MIN
TYP
2.5
15
600
0.2
2
2.55
V
DD
MAX
UNITS
V
ppm/°C
µV/V
Ω
ms
V
V
DD
= 2.7V to 3.6V, V
REF
= 2.5V
Load Current = 0.5mA
Ext C
REF
= 10µF
TYP
MAX
0.6
±10
UNITS
V
V
µA
pF
V
V
V
µA
pF
mA
mA
2.4
5
V
DD
= 3V, I
OUT
= – 200µA
V
DD
= 2.7V, I
OUT
= 160µA
V
DD
= 2.7V, I
OUT
= 1.6mA
V
OUT
= 0V and V
DD
●
●
●
2.5
2.9
0.05
0.4
±10
1
20
15
235112f
3
LTC2351-12
POWER REQUIRE E TS
SYMBOL
V
DD
, V
CC
I
DD
+ I
CC
PARAMETER
Supply Voltage
Supply Current
The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. With internal reference, V
DD
= V
CC
= 3V.
CONDITIONS
Active Mode, f
SAMPLE
= 1.5Msps
Nap Mode
Sleep Mode
Active Mode with SCK, f
SAMPLE
= 1.5Msps
●
●
PD
Power Dissipation
The
●
denotes the specifications which apply over the full operating temperature
range, otherwise specifications are at T
A
= 25°C. V
DD
= 3V.
SYMBOL
f
SAMPLE(MAX)
t
THROUGHPUT
t
SCK
t
CONV
t
1
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
t
10
t
11
PARAMETER
Maximum Sampling Frequency per Channel
(Conversion Rate)
Minimum Sampling Period (Conversion + Acquisiton Period)
Clock Period
Conversion Time
Minimum High or Low SCLK Pulse Width
CONV to SCK Setup Time
SCK Before CONV
Minimum High or Low CONV Pulse Width
SCK↑ to Sample Mode
CONV↑ to Hold Mode
96th SCK↑ to CONV↑ Interval (Affects Acquisition Period)
Minimum Delay from SCK to Valid Bits 0 Through 11
SCK↑ to Hi-Z at SDO
Previous SDO Bit Remains Valid After SCK
V
REF
Settling Time After Sleep-to-Wake Transition
(Note 16)
(Notes 6, 17)
(Note 6)
(Notes 6, 10)
(Note 6)
(Note 6)
(Note 6)
(Notes 6, 11)
(Notes 6, 7, 13)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 12)
(Notes 6, 14)
2
2
CONDITIONS
●
●
●
TI I G CHARACTERISTICS
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
may cause permanent damage to the device. Exposure to any Absolute
Maximum Rating condition for extended periods may affect device
reliabilty and lifetime.
Note 2:
All voltage values are with respect to ground GND.
Note 3:
When these pins are taken below GND or above V
DD
, they will be
clamped by internal diodes. This product can handle input currents greater
than 100mA below GND or greater than V
DD
without latchup.
Note 4:
Offset and range specifications apply for a single-ended CH0
+
–
CH5
+
input with CH0
–
– CH5
–
grounded and using the internal 2.5V
reference.
Note 5:
Integral linearity is tested with an external 2.55V reference and is
defined as the deviation of a code from the straight line passing through
the actual endpoints of a transfer curve. The deviation is measured from
the center of quantization band. Linearity is tested for CH0 only.
Note 6:
Guaranteed by design, not subject to test.
Note 7:
Recommended operating conditions.
Note 8:
The analog input range is defined for the voltage difference
between CHx
+
and CHx
–
, x = 0–5.
4
U W
MIN
2.7
TYP
3.0
5.5
1.5
4.0
16.5
MAX
3.6
8
2
15
UNITS
V
mA
mA
µA
mW
UW
MIN
250
TYP
MAX
UNITS
kHz
4
40
96
2
3
0
4
4
1.2
45
8
6
10000
10000
µs
ns
SCLK cycles
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
Note 9:
The absolute voltage at CHx
+
and CHx
–
must be within this range.
Note 10:
If less than 3ns is allowed, the output data will appear one clock
cycle later. It is best for CONV to rise half a clock before SCK, when
running the clock at rated speed.
Note 11:
Not the same as aperture delay. Aperture delay (1ns) is the
difference between the 2.2ns delay through the sample-and-hold and the
1.2ns CONV to Hold mode delay.
Note 12:
The rising edge of SCK is guaranteed to catch the data coming
out into a storage latch.
Note 13:
The time period for acquiring the input signal is started by the
96th rising clock and it is ended by the rising edge of CONV.
Note 14:
The internal reference settles in 2ms after it wakes up from Sleep
mode with one or more cycles at SCK and a 10µF capacitive load.
Note 15:
The full power bandwidth is the frequency where the output code
swing drops by 3dB with a 2.5V
P-P
input sine wave.
Note 16:
Maximum clock period guarantees analog performance during
conversion. Output data can be read with an arbitrarily long clock period.
Note 17:
The conversion process takes 16 clocks for each channel that is
enabled, up to 96 clocks for all 6 channels.
235112f
LTC2351-12
TYPICAL PERFOR A CE CHARACTERISTICS
SINAD vs Input Frequency
74
71
THD, 2nd, 3rd (dB)
THD, 2nd, 3rd (dB)
68
SINAD (dB)
65
62
59
56
53
0.1
1
FREQUENCY (MHz)
SFDR vs Input Frequency
92
86
80
SFDR (dB)
SNR (dB)
74
68
62
56
50
0.1
MAGNITUDE (dB)
1
FREQUENCY (MHz)
100kHz Bipolar Sine Wave 8192
Point FFT Plot
–0
–10
DIFFERENTIAL LINEARITY (LSB)
–20
–30
MAGNITUDE (dB)
–40
–50
–60
–70
–80
–90
–100
–110
–120
0
25
75
50
FREQUENCY (kHz)
100
125
235112 G07
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
235112 G08
INTEGRAL LINEARITY (LSB)
U W
235112 G01
235112 G04
V
DD
= 3V, T
A
= 25°C
THD, 2nd and 3rd
vs Input Frequency
–50
–56
–62
BIPOLAR SINGLE-ENDED
THD
2nd
THD, 2nd and 3rd
vs Input Frequency
–50
–56
–62
–68
–74
–80
–86
–92
–98
–104
10
UNIPOLAR SINGLE-ENDED
THD
2nd
–68
–74
–80
–86
–92
–98
–104
–100
–116
0.1
3rd
3rd
–110
0.1
1
FREQUENCY (MHz)
10
235112 G02
1
FREQUENCY (MHz)
10
235112 G03
SNR vs Input Frequency
74
71
68
65
62
59
56
53
0.1
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
100kHz Unipolar Sine Wave 8192
Point FFT Plot
10
1
FREQUENCY (MHz)
10
235112 G05
0
25
75
50
FREQUENCY (kHz)
100
125
235112 G06
Differential Linearity vs Output Code,
Unipolar Mode
1
0.8
0.6
1
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1
Integral Linearity vs Output Code,
Unipolar Mode
0
512 1024 1536 2048 2560 3072 3584 4096
OUTPUT CODE
235112 G09
235112f
5
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LTC2351CUH-12#TR Related Products

LTC2351CUH-12#TR LTC2351IUH-12#TR
Description IC 6-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC32, 5 X 5 MM, PLASTIC, MO-220WHHD, QFN-32, Analog to Digital Converter IC 6-CH 12-BIT PROPRIETARY METHOD ADC, SERIAL ACCESS, PQCC32, 5 X 5 MM, PLASTIC, MO-220WHHD, QFN-32, Analog to Digital Converter
Is it lead-free? Contains lead Contains lead
Is it Rohs certified? incompatible incompatible
Maker Linear ( ADI ) Linear ( ADI )
Parts packaging code QFN QFN
package instruction HVQCCN, LCC32,.2SQ,20 HVQCCN, LCC32,.2SQ,20
Contacts 32 32
Reach Compliance Code not_compliant not_compliant
ECCN code EAR99 EAR99
Maximum analog input voltage 2.5 V 2.5 V
Converter type ADC, PROPRIETARY METHOD ADC, PROPRIETARY METHOD
JESD-30 code S-PQCC-N32 S-PQCC-N32
JESD-609 code e0 e0
length 5 mm 5 mm
Maximum linear error (EL) 0.0244% 0.0244%
Humidity sensitivity level 1 1
Number of analog input channels 6 6
Number of digits 12 12
Number of functions 1 1
Number of terminals 32 32
Maximum operating temperature 70 °C 85 °C
Output bit code OFFSET BINARY, 2\'S COMPLEMENT BINARY OFFSET BINARY, 2\'S COMPLEMENT BINARY
Output format SERIAL SERIAL
Package body material PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code HVQCCN HVQCCN
Encapsulate equivalent code LCC32,.2SQ,20 LCC32,.2SQ,20
Package shape SQUARE SQUARE
Package form CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius) 235 235
power supply 3 V 3 V
Certification status Not Qualified Not Qualified
Sampling rate 1.5 MHz 1.5 MHz
Sample and hold/Track and hold SAMPLE SAMPLE
Maximum seat height 0.8 mm 0.8 mm
Nominal supply voltage 3 V 3 V
surface mount YES YES
technology CMOS CMOS
Temperature level COMMERCIAL INDUSTRIAL
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb)
Terminal form NO LEAD NO LEAD
Terminal pitch 0.5 mm 0.5 mm
Terminal location QUAD QUAD
Maximum time at peak reflow temperature 20 20
width 5 mm 5 mm

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【Low Power】Design of Low Power Test Generator Based on FPGA
Design of Low Power Test Generator Based on FPGA...
常见泽1 FPGA/CPLD
TI seems to have a DCDC switching power supply verification platform, which is controlled by DSP and can achieve voltage boost or voltage reduction by controlling different NMOS.
It is a reference design, someone has posted it,It is a digital power supply with multiple NMOS, using DSP to control different NMOS to achieve different topologiesI forgot it now, I wonder if anyone ...
whuer TI Technology Forum
A bluetooth printer implementation solution
Introduction As a short-range wireless communication protocol, Bluetooth technology stands out among many wireless solutions for its low cost, low power consumption, high speed, convenience and flexib...
feifei RF/Wirelessly
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