3.3V CMOS STATIC RAM
1 MEG (64K x 16-BIT)
Integrated Device Technology, Inc.
PRELIMINARY
IDT71V016
FEATURES:
• 64K x 16 advanced high-speed CMOS Static RAM
• Commercial (0˚ to 70˚C) and Industrial (-40˚C to 85˚C)
• Equal access and cycle times
— Commercial and Industrial: 12/15/20ns
• One Chip Select plus one Output Enable pin
• Bidirectional data inputs and outputs directly
TTL-compatible
• Low power consumption via chip deselect
• Upper and Lower Byte Enable Pins
• Single 3.3V(±0.3V) power supply
• Available in 44-pin Plastic SOJ and 44-pin TSOP
package and 48-BALL Plastic FBGA
DESCRIPTION:
The IDT71V016 is a 1,048,576-bit high-speed Static RAM
organized as 64K x 16. It is fabricated using IDT’s high-
perfomance, high-reliability CMOS technology. This state-of-
the-art technology, combined with innovative circuit design
techniques, provides a cost-effective solution for high-speed
memory needs.
The IDT71V016 has an output enable pin which operates
as fast as 7ns, with address access times as fast as 12ns. All
bidirectional inputs and outputs of the IDT71V016 are TTL-
compatible and operation is from a single 3.3V supply. Fully
static asynchronous circuitry is used, requiring no clocks or
refresh for operation.
The IDT71V016 is packaged in a JEDEC standard 44-pin
Plastic SOJ and 44-pin TSOP Type II and 48-BALL 7 x 7 mm
Plastic FBGA .
FUNCTIONAL BLOCK DIAGRAM
OE
Output
Enable
Buffer
A0 - A15
Address
Buffers
Row / Column
Decoders
I/O 15
CS
Chip
Enable
Buffer
8
High
Byte
I/O
Buffer
8
I/O 8
WE
Write
Enable
Buffer
64K x 16
Memory
Array
16
Sense
Amps
and
Write
Drivers
I/O 7
8
Low
Byte
I/O
Buffer
8
I/O 0
BHE
Byte
Enable
Buffers
BLE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
3211 drw 01
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
©1998 Integrated Device Technology, Inc.
JULY 1998
DSC-3211/5
1
IDT71V016
3.3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
A4
A3
A2
A1
A0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
SO44-1
SO44-2
1
A
B
C
D
E
F
G
H
2
3
A
A
A
NC
NC
A
A
A
4
A
A
A
A
NC
A
A
A
5
A
6
NC
I/OL
I/OL
VDD
VSS
I/OL
I/OL
NC
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A5
A6
A7
BLE
I/OH
I/OH
VSS
VDD
I/OH
I/OH
NC
OE
BHE
I/OH
I/OH
I/OH
I/OH
NC
A
CS
I/O 0
I/O 1
I/O 2
I/O 3
VDD
Vss
I/O 4
I/O 5
I/O 6
I/O 7
OE
BHE
BLE
I/O 15
I/O 14
I/O 13
I/O 12
Vss
VDD
I/O 11
I/O 10
I/O 9
I/O 8
NC
A8
A9
A10
A11
NC
3211 drw 02
CS
I/OL
I/OL
I/OL
I/OL
WE
A
3211 drw 03
WE
A15
A14
A13
A12
NC
FBGA
TOP VIEW
PIN DESCRIPTIONS
A
0
– A
15
Address Inputs
Chip Select
Write Enable
Output Enable
High Byte Enable
Low Byte Enable
Data Input/Output
3.3V Power
Ground
Input
Input
Input
Input
Input
Input
I/O
Pwr
Gnd
3211 tbl 01
SOJ/TSOP
TOP VIEW
CS
WE
OE
BHE
BLE
I/O
0
- I/O
15
V
DD
V
SS
TRUTH TABLE
(1)
CS
OE
WE
H
L
L
L
L
L
L
L
L
X
L
L
L
X
X
X
H
X
X
H
H
H
L
L
L
H
X
BLE
X
L
H
L
L
L
H
X
H
BHE
X
H
L
L
L
H
L
X
H
I/O
0
-I/O
7
High-Z
DATA
OUT
High-Z
DATA
OUT
DATA
IN
DATA
IN
High-Z
High-Z
High-Z
I/O
8
-I/O
15
High-Z
High-Z
DATA
OUT
DATA
OUT
DATA
IN
High-Z
DATA
IN
High-Z
High-Z
Function
Deselected - Standby
Low Byte Read
High Byte Read
Word Read
Word Write
Low Byte Write
High Byte Write
Outputs Disabled
Outputs Disabled
3211 tbl 02
NOTE:
1.H = V
IH
, L = V
IL
, X = Don't care.
2
IDT71V016
3.3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
V
TERM
(2)
(3)
Rating
Terminal Voltage with
Respect to GND
Terminal Voltage with
Respect to GND
OperatingTemperature
Temperature Under Bias
Storage Temperature
Power Dissipation
Com’l.
–0.5 to +4.6
Unit
V
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade
Commercial
Temperature
0°C to +70°C
-40°C to +85°C
GND
0V
0V
V
DD
3.3V
±
0.3V
3.3V
±
0.3V
3211 tbl 04
V
TERM
–0.5 to Vcc+0.5V
V
Industrial
T
A
T
BIAS
T
STG
P
T
0 to +70
–55 to +125
–55 to +125
0.6
600mW
50
°C
°C
°C
W
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
V
DD
GND
V
IH
V
IH
Parameter
Supply Voltage
Supply Voltage
Input High Voltage - Inputs
Input High Voltage - I/O
Input Low Voltage
Min. Typ.
3.0
0
2.0
2.0
–0.5
(1)
3.3
0
—
—
—
Max. Unit
3.6
0
4.6
V
DD
+0.3
V
V
V
V
V
I
OUT
DC Output Current
mA
V
IL
0.8
NOTES:
3211 tbl 03
1. Stresses greater than those listed under ABSOLUTE MAXIMUM
RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
DD
terminals only.
3. Input, Output,and I/O terminals; 4.6V maximum.
NOTE:
3211 tbl 05
1. V
IL
(min.) = –1.5V for pulse width less than tRC/2, once per cycle.
CAPACITANCE
(T
A
= +25°C, f = 1.0MHz, SOJ package)
Symbol
C
IN
C
I/O
Parameter
(1)
Input Capacitance
I/O Capacitance
Conditions
V
IN
= 3dV
V
OUT
= 3dV
Max.
6
7
Unit
pF
pF
DC ELECTRICAL CHARACTERISTICS
V
DD
= 3.3V
±
0.3V, Commercial Temperature Range
NOTE:
3211 tbl 06
1. This parameter is guaranteed by device characterization, but not prod-
uction tested.
IDT71V016
Symbol
|I
LI
|
|I
LO
|
V
OL
V
OH
Parameter
Input Leakage Current
Output Leakage Current
Output Low Voltage
Output High Voltage
Test Condition
V
DD
= Max., V
IN
= GND to V
DD
V
DD
= Max.,
CS
= V
IH
, V
OUT
= GND to V
DD
I
OL
= 8mA, V
DD
= Min.
I
OH
= –4mA, V
DD
= Min.
Min.
—
—
—
2.4
Max.
5
5
0.4
—
Unit
µA
µA
V
V
3211 tbl 07
DC ELECTRICAL CHARACTERISTICS
(1)
(V
DD
= 3.3V
±
0.3V, V
LC
= 0.2V, V
HC
= V
DD
–0.2V)
71V016S12
Symbol
I
CC
I
SB
I
SB1
Parameter
Dynamic Operating Current
CS
≤
V
IL
, Outputs Open, V
DD
= Max., f = f
MAX(2)
Standby Power Supply Current (TTL Level)
CS
≥
V
IH
, Outputs Open, V
DD
= Max., f = f
MAX(2)
Standby Power Supply Current (CMOS Level)
CS
≥
V
HC
, Outputs Open, V
DD
= Max., f = 0
(2)
V
IN
≤
V
LC
or V
IN
≥
V
HC
Com’l.
140
40
5
Ind.
140
40
7
71V016S15
Com’l.
130
35
5
Ind.
130
35
7
71V016S20
Com’l.
120
30
5
Ind. Unit
120
30
7
mA
mA
mA
NOTES:
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
); f = 0 means no address input lines are changing .
3211 tbl 08
3
IDT71V016
3.3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
AC TEST CONDITIONS
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
1.5ns
1.5V
1.5V
See Figures 1, 2, and 3
3211 tbl 09
AC TEST LOADS
3.3V
3.3V
320Ω
320Ω
DATA
OUT
DATA
OUT
5pF*
350Ω
30pF*
350Ω
3211 drw 04
3211 drw 05
*Including jig and scope capacitance.
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
7
•
6
∆t
AA,
t
ACS
(Typical, ns) 5
4
3
2
1
•
•
•
•
•
•
8 20 40 60 80 100 120 140 160 180 200
CAPACITANCE (pF)
Figure 3. Output Capacitive Derating
3211 drw 06
4
IDT71V016
3.3V CMOS STATIC RAM 1 MEG (64K x 16-BIT)
INDUSTRIAL AND COMMERCIAL TEMPERATURE RANGES
AC ELECTRICAL CHARACTERISTICS
(V
DD
= 3.3V
±
0.3V, Commercial Temperature Range)
71V016S12
Symbol
Read Cycle
t
RC
t
AA
t
ACS
t
CLZ(1)
t
CHZ(1)
t
OE
t
OLZ(1)
t
OHZ(1)
t
OH
t
BE
t
BLZ
(1)
71V016S15
Min.
15
—
—
5
—
—
0
—
4
—
0
—
15
10
10
10
0
0
10
8
0
1
Max.
—
15
15
—
6
8
—
6
—
8
—
6
—
—
—
—
—
—
—
—
—
—
71V016S20
Min.
20
—
—
5
—
—
0
—
5
—
0
—
20
12
12
12
0
0
12
10
0
1
Max.
—
20
20
—
8
10
—
8
—
10
—
8
—
—
—
—
—
—
—
—
—
—
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Parameter
Read Cycle Time
Address Access Time
Chip Select Access Time
Chip Select Low to Output in Low-Z
Chip Select High to Output in High-Z
Output Enable Low to Output Valid
Output Enable Low to Output in Low-Z
Output Enable High to Output in High-Z
Output Hold from Address Change
Byte Enable Low to Output Valid
Byte Enable Low to Output in Low-Z
Byte Enable High to Output in High-Z
Write Cycle Time
Address Valid to End of Write
Chip Select Low to End of Write
Byte Enable Low to End of Write
Address Set-up Time
Address Hold from End of Write
Write Pulse Width
Data Valid to End of Write
Data Hold Time
Write Enable High to Output in Low-Z
Write Enable Low to Output in High-Z
8
ns
Min.
12
—
—
4
—
—
0
—
4
—
0
—
12
9
9
9
0
0
9
7
0
1
—
Max.
—
12
12
—
6
7
—
6
—
7
—
6
—
—
—
—
—
—
—
—
—
—
6
t
BHZ(1)
Write Cycle
t
WC
t
AW
t
CW
t
BW
t
AS
t
WR
t
WP
t
DW
t
DH
t
OW(1)
t
WHZ(1)
6 —
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
3211 tbl 10
TIMING WAVEFORM OF READ CYCLE NO. 1
(1,2,3)
t
RC
ADDRESS
t
AA
t
OH
DATA
OUT
PREVIOUS DATA
OUT
VALID
t
OH
DATA
OUT
VALID
3211 drw 07
NOTES:
1.
WE
is HIGH for Read Cycle.
2. Device is continuously selected,
CS
is LOW.
3.
OE
,
BHE
, and
BLE
are LOW.
5
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