DATASHEET
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
Description
The IDT2308B is a high-speed phase-lock loop (PLL) clock
multiplier. It is designed to address high-speed clock
distribution and multiplication applications. The zero delay
is achieved by aligning the phase between the incoming
clock and the output clock, operable within the range of 10
to 133 MHz.
The IDT2308B has two banks of four outputs each that are
controlled via two select addresses. By proper selection of
input addresses, both banks can be put in tri-state mode. In
test mode, the PLL is turned off, and the input clock directly
drives the outputs for system testing purposes. In the
absence of an input clock, the IDT2308B enters power
down, and the outputs are tri-stated. In this mode, the
device will draw less than 25µA.
The IDT2308B is available in six unique configurations for
both prescaling and multiplication of the Input REF Clock.
(see Available Options table.)
The PLL is closed externally to provide more flexibility by
allowing the user to control the delay between the input
clock and the outputs.
IDT2308B
Features
•
Phase-Lock Loop Clock Distribution for Applications
ranging from 10 MHz to 133 MHz operating frequency
•
Distributes one clock input to two banks of four outputs
•
Separate output enable for each output bank
•
External feedback (FBK) pin is used to synchronize the
outputs to the clock input
•
•
•
•
•
•
•
Output Skew <200 ps
Low jitter <200 ps cycle-to-cycle
1x, 2x, 4x output options (see Available Options table)
No external RC network required
Operates at 3.3 V V
DD
Available in 16-pin SOIC and TSSOP packages
Available in Commercial and Industrial temperature
ranges
Block Diagram
IDT™
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
1
IDT2308B
REV B 030509
IDT2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
CLOCK MULTIPLIER
Pin Assignment
Applications
•
•
•
•
•
SDRAM
Telecom
Datacom
PC Motherboards/Workstations
Critical Path Delay Designs
Function Table
1
Select Input Decoding
S2
L
L
H
H
S1
L
H
L
H
CLKA
Tri-state
Driven
Driven
Driven
CLKB
Tri-state
Tri-state
Driven
Driven
Output
Source
PLL
PLL
REF
PLL
PLL Shut
Down
Y
N
Y
N
Note 1:
H = HIGH voltage level; L = LOW voltage level
Pin Descriptions
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
REF
1
CLKA1
2
CLKA2
2
VDD
GND
CLKB1
2
CLKB2
2
S2
3
S1
3
CLKB3
2
CLKB4
2
GND
VDD
CLKA3
2
CLKA4
2
FBK
Pin Description
Input Reference Clock, 5 Volt Tolerant Input
Clock Output for Bank A
Clock Output for Bank A
3.3 V Supply
Ground
Clock Output for Bank B
Clock Output for Bank B
Select Input, Bit 2
Select Input, Bit 1
Clock Output for Bank B
Clock Output for Bank B
Ground
3.3 V Supply
Clock Output for Bank A
Clock Output for Bank A
PLL Feedback Input
Notes:
1. Weak pull-down.
2. Weak pull-down on all outputs.
3. Weak pull-up on these inputs.
IDT™
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
2
IDT2308B
REV B 030509
IDT2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
CLOCK MULTIPLIER
Available Options for IDT2308B
Device
IDT2308B-1
IDT2308B-1H
IDT2308B-2
IDT2308B-2
IDT2308B-2H
IDT2308B-2H
IDT2308B-3
IDT2308B-3
IDT2308B-4
IDT2308B-5H
Feedback From
Bank A or Bank B
Bank A or Bank B
Bank A
Bank B
Bank A
Bank B
Bank A
Bank B
Bank A or Bank B
Bank A or Bank B
Bank A Frequency
Reference
Reference
Reference
2 x Reference
Reference
2 x Reference
2 x Reference
4 x Reference
2 x Reference
Reference/2
Bank B Frequency
Reference
Reference
Reference/2
Reference
Reference/2
Reference
Reference or Reference
1
2 x Reference
2 x Reference
Reference/2
Note 1:
Output phase is indeterminant (0° or 180° from input clock).
Absolute Maximum Ratings
1
Symbol
V
DD
V
I2
V
I
I
IK
(V
I
< 0)
I
OK
(V
O
< 0 or V
O
> VDD)
I
O
(V
O
= 0 to VDD)
V
DD
or GND
T
A
= 55 °C (in still air only)
3
T
STG
Operating Temperature
Operating Temperature
Rating
Supply Voltage Range
Input Voltage Range (REF)
Input Voltage Range (except REF)
Input Clamp Current
Terminal Voltage with Respect to
GND (inputs V
IH
2.5, V
IL
2.5)
Continuous Output Current
Continuous Current
Maximum Power Dissipation
Storage Temperature Range
Commercial range
Industrial range
Max.
-0.5 V to +4.6
-0.5 V to +5.5
-0.5 to V
DD
+ 0.5
-50
±50
±50
±100
0.7
-65 to +150
0 to +70
-40 to +85
Unit
V
V
V
mA
mA
mA
mA
W
°
C
°
C
°
C
Notes:
1. Stresses above the ratings listed below can cause permanent damage to the IDT2308B. These ratings, which are standard
values for IDT commercially rated parts, are stress ratings only. Functional operation of the device at these or any other
conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed only over
the recommended operating temperature range.
2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed.
3. The maximum package power dissipation is calculated using a junction temperature of 150°C and a board trace length of 750
mils.
IDT™
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
3
IDT2308B
REV B 030509
IDT2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
CLOCK MULTIPLIER
Zero Delay and Skew Control
To close the feedback loop of the IDT2308B, the FBK pin can be driven from any of the eight available output pins.
The output driving the FBK pin will be driving a total load of 7 pF plus any additional load that it drives. The relative
loading of this output (with respect to the remaining outputs) can adjust the input-output delay.
For applications requiring zero input-output delay, all outputs including the one providing feedback should be
equally loaded. If input-output delay adjustments are required, use the Output Load Difference Chart to calculate
loading differences between the feedback output and remaining outputs. Ensure the outputs are loaded equally, for
zero output-output skew.
IDT™
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
4
IDT2308B
REV B 030509
IDT2308B
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
CLOCK MULTIPLIER
Operating Conditions–Commercial
Symbol
V
DD
T
A
C
L
C
IN
Supply Voltage
Operating Temperature (Ambient Temperature)
Load Capacitance below 100 MHz
Load Capacitance from 100 MHz to 133 MHz
Input
Capacitance
1
Parameter
Conditions
Min.
3
0
–
–
–
Max.
3.6
70
30
15
7
Units
V
°C
pF
pF
pF
Note 1:
Applies to both REF and FBK.
DC Electrical Characteristics–Commercial
Parameter
Input High Voltage Level
Input Low Voltage Level
Input Low Current
Input High Current
Output High Voltage
Output Low Voltage
Power Down Current
Symbol
V
IH
V
IL
I
IL
I
IH
V
OH
V
OL
I
DD_PD
V
IN
= 0V
V
IN
= V
DD
Conditions
Min.
2
Typ.
Max.
0.8
50
100
Units
V
V
µA
µA
V
I
OH
= -8 mA (-1, -2, -3, -4)
I
OH
= -12 mA (-1H, -2H, -5H)
I
OL
= 8 mA (-1, -2, -3, -4)
I
OL
= 12 mA (-1H, -2H, -5H)
REF = 0MHz (S2 = S1 = H)
100 MHz CLKA (-1, -2, -3, -4)
100 MHz CLKA (-1H, -2H, -5H)
Unloaded Outputs
Select Inputs at V
DD
or
GND
66 MHz CLKA (-1, -2, -3, -4)
66 MHz CLKA (-1H, -2H, -5H)
33 MHz CLKA (-1, -2, -3, -4)
33 MHz CLKA (-1H, -2H, -5H)
2.4
0.4
12
45
70
32
50
18
30
V
µA
Supply Current
I
DD
mA
IDT™
3.3 VOLT ZERO DELAY CLOCK MULTIPLIER
5
IDT2308B
REV B 030509
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