W3EG6466S335AD4SG datasheet, PDF

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W3EG6466S335AD4SG: DescriptionDDR DRAM Module, 64MX64, 0.7ns, CMOS, ROHS COMPLIANT, SO-DIMM-200; Categorystorage storage; File Size210KB，13 Pages; ManufacturerMicrosemi; Websitehttps://www.microsemi.com; Environmental Compliance

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W3EG6466S335AD4SG Overview

DDR DRAM Module, 64MX64, 0.7ns, CMOS, ROHS COMPLIANT, SO-DIMM-200

W3EG6466S335AD4SG Parametric

Parameter Name	Attribute value
Is it lead-free?	Lead free
Is it Rohs certified?	conform to
Maker	Microsemi
Parts packaging code	MODULE
package instruction	DIMM,
Contacts	200
Reach Compliance Code	unknown
ECCN code	EAR99
access mode	DUAL BANK PAGE BURST
Maximum access time	0.7 ns
Other features	AUTO/SELF REFRESH
JESD-30 code	R-XDMA-N200
memory density	4294967296 bit
Memory IC Type	DDR DRAM MODULE
memory width	64
Number of functions	1
Number of ports	1
Number of terminals	200
word count	67108864 words
character code	64000000
Operating mode	SYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	64MX64
Package body material	UNSPECIFIED
encapsulated code	DIMM
Package shape	RECTANGULAR
Package form	MICROELECTRONIC ASSEMBLY
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
Certification status	Not Qualified
self refresh	YES
Maximum supply voltage (Vsup)	2.7 V
Minimum supply voltage (Vsup)	2.3 V
Nominal supply voltage (Vsup)	2.5 V
surface mount	NO
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	NO LEAD
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED

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White Electronic Designs

W3EG6466S-AD4

-BD4

PRELIMINARY*

512MB – 2x32Mx64 DDR SDRAM UNBUFFERED, w/PLL

FEATURES

DDR200, DDR266 and DDR333

• JEDEC design speciﬁcations

Double-data-rate architecture

Bi-directional data strobes (DQS)

Differential clock inputs (CK & CK#)

Programmable Read Latency 2,2.5 (clock)

Programmable Burst Length (2,4,8)

Programmable Burst type (sequential & interleave)

Edge aligned data output, center aligned data input

Auto and self refresh

Serial presence detect

Dual Rank

Power supply: 2.5V ± 0.20V

JEDEC standard 200 pin SO-DIMM package

• Package height options:

AD4: 35.5mm (1.38")

BD4: 31.75mm (1.25")

NOTE: Consult factory for availability of:

• RoHS compliant products

• Vendor source control options

• Industrial temperature option

* This product is under development, is not qualiﬁed or characterized and is subject to

change without notice.

DESCRIPTION

The W3EG6466S is a 2x32Mx64 Double Data Rate

SDRAM memory module based on 512Mb DDR SDRAM

components. The module consists of sixteen 32Mx8

components as eight 64Mx8 stacked DDR SDRAMs

in 66 pin TSOP packages mounted on a 200 pin FR4

substrate.

Synchronous design allows precise cycle control with the

use of system clock. Data I/O transactions are possible on

both edges and Burst Lengths allow the same device to be

useful for a variety of high bandwidth, high performance

memory system applications.

OPERATING FREQUENCIES

DDR333 @CL=2.5

Clock Speed

CL-t

RCD

-t

166MHz

2.5-3-3

DDR266 @CL=2

133MHz

2-2-2

DDR266 @CL=2.5

133MHz

2.5-3-3

DDR200 @CL=2

100MHz

2-2-2

White Electronic Designs Corp. reserves the right to change products or speciﬁcations without notice.

January 2005

Rev. 2

White Electronic Designs Corporation • (602) 437-1520 • www.whiteedc.com

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