P4C1256L
LOW POWER 32K X 8
STATIC CMOS RAM
FEATURES
V
CC
Current (Commercial/Industrial)
— Operating: 70mA/85mA
— CMOS Standby: 100µA/100µA
Access Times
—55/70/85
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using
CE
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
— 28-Pin 600 mil DIP
— 28-Pin 300 mil CERDIP
— 28-Pin 300 mil Narrow Body SOP
— 28-Pin 330 mil SOP
— 28-Pin LCC (350x550mil)
— 32-Pin LCC (450x550mil)
DESCRIPTION
The P4C1256L is a 262,144-bit low power CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times of 55 ns and 70 ns are available. CMOS is
utilized to reduce power consumption to a low level.
The P4C1256L device provides asynchronous operation
with matching access and cycle times. Memory locations
are specified on address pins A
0
to A
14
. Reading is accom-
plished by device selection (CE and output enabling (OE)
while write enable (WE) remains HIGH. By presenting the
address under these conditions, the data in the addressed
memory location is presented on the data input/output pins.
The input/output pins stay in the HIGH Z state when either
CE
or
OE
is HIGH or
WE
is LOW.
FUNCTIONAL BLOCK DIAGRAM
PIN CONFIGURATIONS
DIP (P6, D5-2), SOP (S11-2, S11-3)
TOP VIEW
LCC PIN CONFIGURATIONS AT END OF DATASHEET
Document #
SRAM121
REV G
Revised July 2012
P4C1256L - 32K x 8 STATIC CMOS RAM
RECOMMENDED OPERATING TEMPERATURE AND SUPPLY VOLTAGE
Temperature Range (Ambient)
Commercial (0°C to 70°C)
Industrial (-40°C to 85°C)
Military (-55°C to 125°C)
Supply Voltage
4.5V ≤ V
CC
≤ 5.5V
4.5V ≤ V
CC
≤ 5.5V
4.5V ≤ V
CC
≤ 5.5V
MAXIMUM RATINGS
(1)
Sym
V
CC
V
TERM
T
A
S
TG
I
OUT
I
LAT
Parameter
Supply Voltage with Respect to GND
Terminal Voltage with Respect to GND (up to 7.0V)
Operating Ambient Temperature
Storage Temperature
Output Current into Low Outputs
Latch-up Current
> 200
Min
-0.5
-0.5
-55
-65
Max
7.0
V
CC
+ 0.5
125
150
25
Unit
V
V
°C
°C
mA
mA
DC ELECTRICAL CHARACTERISTICS
Sym Parameter
V
OH
V
OL
V
IH
V
IL
I
LI
Output High Voltage (I/O
0
- I/O
7
)
Output Low Voltage (I/O
0
- I/O
7
)
Input High Voltage
Input Low Voltage
(Over Recommended Operating Temperature & Supply Voltage)
(2)
Test Conditions
I
OH
= -1mA, V
CC
= 4.5V
I
OL
= 2.1mA
2.2
-0.5
(3)
Com
Input Leakage Current
GND ≤ V
IN
≤ V
CC
Ind
Mil
GND ≤ V
OUT
≤ V
CC
CE
= V
IH
V
CC
= 5.5V, I
OUT
= 0 mA
CE
= V
IH
V
CC
= 5.5V, I
OUT
= 0 mA
CE
≥ V
CC
- 0.2V
Com
Ind
Mil
3
mA
-2
-5
+2
+5
µA
-2
-5
Min
2.4
0.4
V
CC
+ 0.3
0.8
+2
+5
µA
Max
Unit
V
V
V
V
I
LO
Output Leakage Current
V
CC
Current
TTL Standby Current
(TTL Input Levels)
V
CC
Current
CMOS Standby Current
(CMOS Input Levels)
I
SB
I
SB1
100
µA
N/A = Not applicable
Document #
SRAM121
REV G
Page 2
P4C1256L - 32K x 8 STATIC CMOS RAM
CAPACITANCES
(4)
Symbol
C
IN
C
OUT
(V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz)
Parameter
Input Capacitance
Output Capacitance
Test Conditions
V
IN
=0V
V
OUT
=0V
Max
7
9
Unit
pF
pF
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Sym
Parameter
Temperature Range
Commercial
I
CC
Dynamic Operating Current*
Industrial
Military
*
-55
70
85
100
-70
70
85
100
-85
70
85
100
-55
15
25
35
**
-70
15
25
35
-85
15
25
35
Unit
mA
mA
mA
* Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously
enabled for writing, i.e.
CE
and
WE
≤ V
IL
(max),
OE
is high. Switching inputs are 0V and 3V.
** As above but @ f=1 MHz and V
IL
/V
IH
= 0V/V
CC
.
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Sym
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
t
PU
t
PD
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable Low to Data Valid
Output Enable Low to Low Z
Output Enable High to High Z
Chip Enable to Power Up Time
Chip Disable to Power Down Time
0
55
5
20
0
70
5
5
20
30
5
25
0
85
-55
Min
55
55
55
5
5
25
35
5
30
Max
Min
70
70
70
5
5
30
40
-70
Max
Min
85
85
85
-85
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #
SRAM121
REV G
Page 3
P4C1256L - 32K x 8 STATIC CMOS RAM
TIMING WAVEFORM OF READ CYCLE NO. 1 (OE CONTROLLED)
(5)
TIMING WAVEFORM OF READ CYCLE NO. 2 (ADDRESS CONTROLLED)
(5,6)
TIMING WAVEFORM OF READ CYCLE NO. 3 (ADDRESS CONTROLLED)
(5,7)
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
5.
WE
is HIGH for READ cycle.
6.
CE
is LOW and
OE
is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with
CE
transition LOW.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is sampled
and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM121
REV G
Page 4
P4C1256L - 32K x 8 STATIC CMOS RAM
AC CHARACTERISTICS—WRITE CYCLE
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Parameter
Write Cycle Time
Chip Enable Time to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Address Hold Time
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write
(Over Recommended Operating Temperature & Supply Voltage)
-55
Min
55
50
50
0
40
0
25
0
25
5
5
Max
Min
70
60
60
0
50
0
30
0
30
5
-70
Max
Min
85
75
75
0
60
0
35
0
35
-85
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMING WAVEFORM OF WRITE CYCLE NO. 1 (WE CONTROLLED)
(10,11)
Notes:
10.
CE
and
WE
must be LOW for WRITE cycle.
11.
OE
is LOW for this WRITE cycle to show t
WZ
and t
OW
.
12. If
CE
goes HIGH simultaneously with
WE
HIGH, the output remains
in a high impedance state
13. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM121
REV G
Page 5
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