IDT72142S35L datasheet, PDF - EEWORLD Datasheet

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IDT72142S35L: DescriptionFIFO, 4KX9, 35ns, Asynchronous, CMOS, CQCC32, LCC-32; Categorystorage storage; File Size121KB，11 Pages; ManufacturerIDT (Integrated Device Technology)

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IDT72142S35L Overview

FIFO, 4KX9, 35ns, Asynchronous, CMOS, CQCC32, LCC-32

IDT72142S35L Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	QFJ
package instruction	LCC-32
Contacts	32
Reach Compliance Code	not_compliant
ECCN code	EAR99
Maximum access time	35 ns
Other features	RETRANSMIT
Maximum clock frequency (fCLK)	22.2 MHz
period time	45 ns
JESD-30 code	R-CQCC-N32
JESD-609 code	e0
memory density	36864 bit
Memory IC Type	OTHER FIFO
memory width	9
Number of functions	1
Number of terminals	32
word count	4096 words
character code	4000
Operating mode	ASYNCHRONOUS
Maximum operating temperature	70 °C
Minimum operating temperature
organize	4KX9
Output characteristics	3-STATE
Exportable	YES
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	QCCN
Encapsulate equivalent code	LCC32,.45X.55
Package shape	RECTANGULAR
Package form	CHIP CARRIER
Parallel/Serial	PARALLEL
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	5 V
Certification status	Not Qualified
Maximum standby current	0.008 A
Maximum slew rate	0.14 mA
Maximum supply voltage (Vsup)	5.5 V
Minimum supply voltage (Vsup)	4.5 V
Nominal supply voltage (Vsup)	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	NO LEAD
Terminal pitch	1.27 mm
Terminal location	QUAD
Maximum time at peak reflow temperature	NOT SPECIFIED

IDT72142S35L Preview

CMOS SERIAL-TO-PARALLEL FIFO

2,048 x 9 and 4,096 x 9

Integrated Device Technology, Inc.

IDT72132

IDT72142

FEATURES:

• 35ns parallel-port access time, 45ns cycle time

• 50MHz serial port shift rate

• Expandable in depth and width with no external

components

• Programmable word lengths including 8, 9, 16-18, and

32-36 bit using Flexshift™ serial input without using any

additional components

• Multiple status flags: Full, Almost-Full (1/8 from full),

Half-Full, Almost Empty (1/8 from empty), and Empty

• Asynchronous and simultaneous read and write

operations

• Dual-Port zero fall-through architecture

• Retransmit capability in single device mode

• Produced with high-performance, low-power CMOS

technology

• Available in the 28-pin plastic DIP

• Industrial temperature range (–40

C to +85

DESCRIPTION:

The IDT72132/72142 are high-speed, low-power serial-to-

parallel FIFOs. These FIFOs are ideally suited to serial

communications applications, tape/disk controllers, and local

area networks (LANs). These devices can be configured with

the IDTs parallel-to-serial FIFOs (IDT72131/72141) for bidi-

rectional serial data buffering.

The FIFO has a serial input port and a 9-bit parallel output

port. Wider and deeper serial-to-parallel data buffers can be

built using multiple IDT72132/72142 chips. IDTs unique

Flexshift serial expansion logic (SIX,

) makes width

expansion possible with no additional components. These

FIFOs will expand to a variety of word widths including 8, 9, 16,

and 32 bits. These devices can also be directly connected for

depth expansion.

Five flags are provided to monitor the FIFO. The Full and

Empty flags prevent any FIFO data overflow or underflow

conditions. The Almost-Full (7/8), Half-Full, and Almost-Empty

(1/8) flags signal memory utilization within the FIFO.

The IDT72132/72142 is fabricated using IDTs high-speed

submicron CMOS technology.

FUNCTIONAL BLOCK DIAGRAM

SICP

SIX

PIN CONFIGURATION

Vcc

SERIAL INPUT

CIRCUITRY

FLAG

LOGIC

GND

NEXT WRITE

POINTER

RAM ARRAY

2,048 x 9

4,096 x 9

READ

POINTER

GND

SICP

SIX

RESET

LOGIC

GND

EXPANSION

LOGIC

-Q

2752 drw 01

2752 drw 02

PLASTIC DIP (P28-1, order code: P)

TOP VIEW

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

INDUSTRIAL TEMPERATURE RANGE

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

OCTOBER 1999

DSC-2752/-

IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO

2,048 x 9, 4,096 x 9

INDUSTRIAL TEMPERATURE RANGE

PIN DESCRIPTIONS

Symbol

Name

Serial Input

Reset

I/O

Description

Serial data is shifted in least significant bit first. In the serial cascade mode, the Serial Input

(SI) pins are tied together and SIX plus D

, D

determine which device stores the data.

When

is set LOW, internal READ and WRITE pointers are set to the first location of the

RAM array.

and

go HIGH, and

AEF

, and

go LOW. A reset is required before an initial

WRITE after power-up.

must be HIGH during an

cycle.

To program the Serial In word width , connect

with one of the Data Set pins (D

, D

Serial data is read into the serial input register on the rising edge of SICP. In both Depth and

Serial Word Width Expansion modes, all of the SICP pins are tied together.

When READ is LOW, data can be read from the RAM array sequentially, independent of SICP.

In order for READ to be active,

must be HIGH. When the FIFO is empty (

-LOW), the

internal READ operation is blocked and Q

-Q

are in a high impedance condition.

This is a dual-purpose input. In the single device configuration (

grounded), activating

retransmit (

-LOW) will set the internal READ pointer to the first location. There is no

effect on the WRITE pointer.

must be HIGH and SICP must be LOW before setting

LOW. Retransmit is not possible in depth expansion. In the depth expansion configuration,

grounded indicates the first activated device.

In the single device configuration,

is grounded. In depth expansion or daisy chain

expansion,

is connected to

(expansion out) of the previous device.

SICP

Next Write

Serial Input Clock

Read

First Load/

Retransmit

SIX

Expansion In

Serial Input

Expansion

In the Expansion mode, the SIX pin of the least significant device is tied HIGH. The SIX pin

of all other devices is connected to the D

or D

pin of the previous device. For single device

operation, SIX is tied HIGH.

When

is set LOW, the parallel output buffers receive data from the RAM array. When

is set HIGH, parallel three state buffers inhibit data flow.

Data outputs for 9-bit wide data.

When

goes LOW, the device is full and data must not be clocked by SICP. When

HIGH, the device is not full. See the diagram on page 7 for more details.

–Q

Output Enable

Output Data

Full Flag

Empty Flag

Almost-Empty/

Almost-Full Flag

Expansion Out/

Half-Full Flag

AEF

When

goes LOW, the device is empty and further READ operations are inhibited. When

is HIGH, the device is not empty.

When

AEF

is LOW, the device is empty to 1/8 full or 7/8 to completely full. When

AEF

is HIGH,

the device is greater than 1/8 full, but less than 7/8 full.

This is a dual-purpose output. In the single device configuration (

grounded), the device is

more than half full when

is LOW. In the depth expansion configuration (

connected to

of the next device), a pulse is sent from

when the last location in the RAM array

is filled.

, D

Data Set

The appropriate Data Set pin (D

, D

) is connected to

to program the Serial In data word

width. For example: D

programs a 8-bit word width, D

programs a 9-bit word

width, etc.

Single Power Supply of 5V.

Three grounds at 0V.

2752 tbl 01

GND

Power Supply

Ground

STATUS FLAGS

Number of Words in FIFO

IDT72132

1-255

256-1,024

1,025-1,792

1,793-2,047

2,048

IDT72142

1-511

512-2,048

2,049-3,584

3,585-4,095

4,096

AEF

2752 tbl 02

IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO

2,048 x 9, 4,096 x 9

INDUSTRIAL TEMPERATURE RANGE

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

TERM

STG

OUT

Rating

Terminal Voltage with

Respect to GND

Storage Temperature

DC Output Current

–55 to +125

–50 to +50

°C

Commercial

–0.5 to +7.0

Unit

RECOMMENDED DC OPERATING CONDITIONS

Symbol

GND

IL(1)

Parameter

Commercial Supply

Voltage

Supply Voltage

Input High Voltage

Commercial

Input Low Voltage

Min.

4.5

2.0

—

Typ.

5.0

—

Max. Unit

5.5

—

0.8

+85

°C

2752 tbl 04

NOTE:

2752 tbl 03

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a stress

rating only and functional operation of the device at these or any other

conditions above those indicated in the operational sections of this

specification is not implied. Exposure to absolute maximum rating

conditions for extended periods may affect reliability.

Operating Temperature -40

Industrial

NOTE:

1. 1.5V undershoots are allowed for 10ns once per cycle.

CAPACITANCE

= +25°C, f = 1.0MHz)

Symbol

OUT

Parameter

Input Capacitance

Output Capacitance

Conditions

= 0V

OUT

= 0V

Max.

Unit

2752 tbl 05

NOTE:

1. Characterized values, not currently tested.

DC ELECTRICAL CHARACTERISTICS

(Industrial: V

= 5.0V

10%, T

= -40°C to +85°C)

IDT72132

IDT72142

Industrial

Symbol

(1)

(2)

CC1

(3)

CC2

(3,4)

CC3

(3,4)

Parameter

Input Leakage Current

(Any Input)

Output Leakage Current

Output Logic "1" Voltage,

OUT

= –2mA

Output Logic "0" Voltage,

OUT

= 8mA

Active Power Supply Current

Standby Current

(

= V

; SICP = V

)

Power Down Current

Min.

–1

–10

2.4

—

Typ.

—

Max.

—

0.4

140

Unit

µA

2752 tbl 06

NOTES:

1. Measurements with 0.4

≤

2. R

≤

, 0.4

≤

OUT

≤

3. Tested with outputs open (I

OUT

= 0).

= V

-0.2V; SICP

≤

0.2V; all other inputs = V

- 0.2V or GND + 0.2V, which toggle at 20 MHz.

IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO

2,048 x 9, 4,096 x 9

INDUSTRIAL TEMPERATURE RANGE

AC ELECTRICAL CHARACTERISTICS

(Industrial: V

= 5.0V

10%, T

= -40°C to +85°C)

Industrial

IDT72132L35

IDT72132L50

IDT72142L35

IDT72142L50

Min.

Max.

Min.

Max.

—

22.2

—

Symbol

Parameter

Parallel Shift Frequency

SICP

Serial-InShift Frequency

PARALLEL OUTPUT TIMINGS

Access Time

Read Recovery Time

RPW

Read Pulse Width

Read Cycle Time

RLZ

Read Pulse LOW to Data Bus at Low-Z

(1)

RHZ

Read Pulse HIGH to Data Bus at High-Z

(1)

Data Valid from Read Pulse HIGH

OEHZ

Output Enable to High-Z (Disable)

(1)

OELZ

Output Enable to Low-Z (Enable)

(1)

AOE

Output Enable to Data Valid (Q

0-8

)

SERIAL INPUT TIMINGS

SIS

Serial Data in Set-Up Time to SICP Rising Edge

SIH

Serial Data in Hold Time to SICP Rising Edge

SIX

SIX Set-Up Time to SICP Rising Edge

SICW

Serial-In Clock Width HIGH/LOW

FLAG TIMINGS

SICEF

SICP Rising Edge (Last Bit - First Word) to

HIGH

SICFF

SICP Rising Edge (Bit 1 - Last Word) to

LOW

SICF

SICP Rising Edge to

AEF

RFFSI

Recovery Time SICP After

Goes HIGH

REF

Read LOW to

LOW

RFF

Read HIGH to

HIGH

Read HIGH to Transitioning

and

AEF

RPE

Read Pulse Width After

HIGH

RESET TIMINGS

RSC

Reset Cycle Time

Reset Pulse Width

RSS

Reset Set-up Time

RSR

Reset Recovery Time

RSF1

Reset to

and

AEF

LOW

RSF2

Reset to

and

HIGH

RSDL

Reset to D LOW

POI

SICP Rising Edge to D

RETRANSMIT TIMINGS

RTC

Retransmit Cycle Time

Retransmit Pulse Width

RTS

Retransmit Set-up Time

RTR

Retransmit Recovery Time

DEPTH EXPANSION MODE TIMINGS

XOL

Read/Write to

LOW

XOH

Read/Write to

HIGH

Pulse Width

XIR

Recovery Time

XIS

Set-up Time

NOTE:

1. Guaranteed by design minimum times, not tested

Unit

MHz

2752 tbl 07

IDT72132, IDT72142 CMOS SERIAL-TO-PARALLEL FIFO

2,048 x 9, 4,096 x 9

INDUSTRIAL TEMPERATURE RANGE

AC TEST CONDITIONS

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

5ns

1.5V

See Figure A

2752 tbl 08

1.1KΩ

D.U.T.

680Ω

30pF*

2752 drw 03

or equivalent circuit

Figure A. Output Load

*Includies jig and scope capacitances

FUNCTIONAL DESCRIPTION

Serial Data Input

The serial data is input on the SI pin. The data is clocked

in on the rising edge of SICP providing the Full Flag (

) is not

asserted. If the Full Flag is asserted then the next parallel data

word is inhibited from moving into the RAM array. NOTE:

SICP should not be clocked once the last bit of the last word

has been shifted in, as indicated by

HIGH and

LOW.

If it is, then the input data will be lost.

The serial word is shifted in Least Significant Bit first. Thus,

when the FIFO is read, the Least Significant Bit will come out

on Q

and the second bit is on Q

and so on. The serial word

width must be programmed by connecting the appropriate

Data Set line (D

, D

) to the

input. The data set lines are

taps off a digital delay line. Selecting one of these taps

programs the width of the serial word to be written in.

Parallel Data Output

A read cycle is initiated on the falling edge of Read (

)

provided the Empty Flag is not set. The output data is

accessed on a first-in/first-out basis, independent of the

ongoing write operations. The data is available t

after the

falling edge of

and the output bus Q goes into high imped-

ance after

goes HIGH.

Alternately, the user can access the FIFO by keeping

LOW and enabling data on the bus by asserting Output

Enable (

). When

is LOW, the

signal enables data on

the output bus. When

is LOW and

is HIGH, the output

bus is three-stated. When

is HIGH, the output bus is

disabled irrespective of

RSC

RSS

SICP

RSS

RSR

n-1

(1)

RSF1

RSF2

RSDL

2752 drw 04

PDI

NOTE:

1. Input bits are numbered 0 to n-1. D

and D

correspond to n=8 and n=9 respectively

Figure 1. Reset

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