Z87010VSC datasheet, PDF - EEWORLD Datasheet

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Z87010VSC: DescriptionDigital Signal Processor, 16-Ext Bit, 20MHz, CMOS, PQCC44, PLASTIC, LCC-44; CategoryThe embedded processor and controller Microcontrollers and processors; File Size83KB，22 Pages; ManufacturerZilog, Inc.; Websitehttps://www.zilog.com/

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Z87010VSC Overview

Digital Signal Processor, 16-Ext Bit, 20MHz, CMOS, PQCC44, PLASTIC, LCC-44

Z87010VSC Parametric

Parameter Name	Attribute value
Maker	Zilog, Inc.
Parts packaging code	LCC
package instruction	QCCJ,
Contacts	44
Reach Compliance Code	unknown
Address bus width	3
barrel shifter	NO
boundary scan	NO
maximum clock frequency	20 MHz
External data bus width	16
Format	FIXED POINT
Internal bus architecture	MULTIPLE
JESD-30 code	S-PQCC-J44
length	16.5862 mm
Number of terminals	44
Maximum operating temperature	70 °C
Minimum operating temperature	-20 °C
Package body material	PLASTIC/EPOXY
encapsulated code	QCCJ
Package shape	SQUARE
Package form	CHIP CARRIER
Certification status	Not Qualified
Maximum seat height	4.57 mm
Maximum supply voltage	5.5 V
Minimum supply voltage	4.5 V
Nominal supply voltage	5 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal form	J BEND
Terminal pitch	1.27 mm
Terminal location	QUAD
width	16.5862 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, OTHER

Z87010VSC Preview

P

RELIMINARY

P

RODUCT

S

PECIFICATION

2

Z87010/Z87L10

A

UDIO

E

NCODER

/D

ECODERS

FEATURES

Device

Z87010

Z87L10

ROM

(Kbyte)

4

I/O

Lines

16

Package

Information

44-Pin PLCC

44-Pin QFP

s

2

Direct Interface to 8-Bit

µ

-law Telephone CODEC

I/O Bus (16-Bit Tristable Data, 3-Bit Address)

Wait State Generator

Two External Interrupts

Four Separate I/O Pins (2 Input, 2 Output)

Hardware

s

16-Bit DSP Processor

3.0V to 3.6V; -20

°

to +70

°

C, Z87L10

4.5V to 5.5V, -20

°

to +70

°

C, Z87010

Static Architecture

512 Word On-Chip RAM

Modified Harvard Architecture

Direct Interface to Z87000

Spreader/Despreader

Frequency

Hopping

Software

s

Full Duplex 32 Kbps ADPCM Encoding/Decoding

Single Tone and DTMF Signal Generation

Sidetone, Volume Control, Mute Functions

Large Phone Number Memory (21 numbers of 23 digits

each)

Master-Slave Protocol Interface to Z87000 Spreader/-

Despreader

s

GENERAL DESCRIPTION

The Z87010/Z87L10 is a second generation CMOS Digital

Signal Processor (DSP) that has been ROM-coded by

Zilog to provide full-duplex 32 Kbps, Adaptive Delta Pulse

Code Modulation (ADPCM) speech coding/decoding (CO-

DEC), and interface to the Z87000/Z87L00 Spread Spec-

trum Cordless Telephone Controller. Together the

Z87000/Z87L00 and Z87010/Z87L10 devices support the

implementation of a 900 MHz frequency-hopping spread

spectrum cordless telephone in conformance with United

States FCC regulations for unlicensed operation.

The Z87010 and Z87L10 are distinct 5V and 3.3V versions

of the ADPCM Audio Encoder/Decoder. For the sake of

brevity, all subsequent references to the Z87010 in this

document also are applicable to the Z87L10, unless spe-

cifically noted.

The Z87010’s single cycle instruction execution and Har-

vard bus structure promote efficient algorithm execution.

The processor contains a 4K word program ROM and 512

word data RAM. Six dual operand fetching. Three vectored

interrupts are complemented by a six level stack. The CO-

DEC interface enables high-speed transfer rate to accom-

modate digital audio and voice data. A dedicated

Counter/Timer provides the necessary timing signals for

the CODEC interface. An additional 13-bit timer is dedicat-

ed for general-purpose use.

The Z87010’s circuitry is optimized to accommodate intri-

cate signal processing algorithms and is used here for

speech compression/decompression, generation of DTMF

tones and other cordless telephone functions. Dedicated

hardware allows direct interface to a variety of CODEC

DS96WRL0601

PRELIMINARY

2-1

Z87010/Z87L10

Audio Encoder/Decoders

Zilog

GENERAL DESCRIPTION

(Continued)

ICs. As configured by the Zilog-provided embedded soft-

ware for digital cordless phones, the Z87010 supports a

low-cost 8-bit

µ

-law telephone CODEC. The Z87010 is to

be used with the Z87000 and operates at 16.384 MHz, pro-

viding 16 MIPS of processing power needed for the cord-

less telephone application.

RXD

256 Word

RAM0

EXT 0-15

/RDYE

ER//W

/EI

EA0-2

Wait

State

Generator

13-Bit

Timer

Power

4K Words

Program ROM

16-Bit

I/O

Interface

256 Word

RAM1

Dual

CODEC

Interface

TXD

SCLK

FS0

FS1

DSP

Core

UO0-1

UI0-1

/RESET

/INT0-2

VDD

VSS

Figure 1. Z87010 Functional Block Diagram

Notes:

All signals with a preceding front slash, ‘/’, are

active Low, e.g., B//W (WORD is active Low); /B/W (BYTE

is active Low, only).

Power connections follow conventional descriptions be-

low:

Connection

Power

Ground

Circuit

V

CC

GND

Device

V

DD

V

SS

2-2

PRELIMINARY

DS96WRL0601

Zilog

Z87010/Z87L10

Audio Encoder/Decoders

PIN DESCRIPTION

2

VSS

EXT0

EXT1

EXT2

VSS

RXD

EXT12

EXT13

EXT14

VSS

EXT15

7

FS1

UO1

UO0

/INTO

FSO

HALT

CLK

/DS

VDD

EA2

EA1

6

1

40

39

EA0

/RESET

WAIT

RD//WR

VDD

SCLK

UI0

UI1

/INT1

/INT2

EXT11

Z87010

17

18

29

28

Figure 2. 44-Pin PLCC Pin Assignments

DS96WRL0601

EXT3

EXT4

VSS

EXT5

EXT6

EXT7

TXD

EXT8

EXT9

VSS

EXT10

PRELIMINARY

2-3

Z87010/Z87L10

Audio Encoder/Decoders

Zilog

PIN DESCRIPTION

(Continued)

Table 1. 44-Pin PLCC Pin Identiﬁcation

No.

1

2

3

4-5

6

7,11,16,20,27

8-10

12

13-15

17

18-19

21-23

24

25-26

28-29

30

31

32

33

34

35,42

36

37

38

39-41

43

44

HALT

FS0

/INT0

UO0-UO1

FS1

V

SS

EXT0-EXT2

RXD

EXT12-EXT14

EXT15

EXT3-EXT4

EXT5-EXT7

TXD

EXT8-EXT9

EXT10-EXT11

/INT2

/INT1

UI1

UI0

SCLK

V

DD

RD//WR

WAIT

/RESET

EA0-EA2

/DS

CLK

Symbol

Function

Stop execution

CODEC0 frame sync

Interrupt

User output

CODEC1 frame sync

Ground

External data bus

Serial input from CODECs

External data bus

Serial output to CODECs

External data bus

Interrupt

User input

CODEC serial clock

Power supply

RD /WR strobe for EXT bus

WAIT state

Reset

External address bus

Data strobe for external bus

Clock

Direction

Input

Input/Output*

Input

Output

Input/Output*

Input/Output

Input

Input/Output

Output

Input/Output

Input

Input/Output*

Input

Output

Input

Output

Input

Note:

*Defined input or output by interface mode selection

2-4

PRELIMINARY

DS96WRL0601

Zilog

Z87010/Z87L10

Audio Encoder/Decoders

33

VSS

EXT0

EXT1

EXT2

VSS

RXD

EXT12

EXT13

EXT14

VSS

EXT15

34

FS1

UO1

UO0

/INT0

FSO

HALT

CK

/EI

VDD

EA2

EA1

2

EA0

/RES

/RDYE

ER//W

VDD

SCLK

UI0

UI1

/INT1

/INT2

EXT11

23

22

Z87010

44

1

12

11

Figure 3. 44-Pin QFP Pin Assignments

DS96WRL0601

EXT3

EXT4

VSS

EXT5

EXT6

EXT7

TXD

EXT8

EXT9

VSS

EXT10

PRELIMINARY

2-5

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Z87010VSC Related Products

	Z87010VSC	Z87L10FSC	Z87010FSC
Description	Digital Signal Processor, 16-Ext Bit, 20MHz, CMOS, PQCC44, PLASTIC, LCC-44	Digital Signal Processor, 16-Ext Bit, 20MHz, CMOS, PQFP44, QFP-44	Digital Signal Processor, 16-Ext Bit, 20MHz, CMOS, PQFP44, QFP-44
Maker	Zilog, Inc.	Zilog, Inc.	Zilog, Inc.
Parts packaging code	LCC	QFP	QFP
package instruction	QCCJ,	QFP,	QFP,
Contacts	44	44	44
Reach Compliance Code	unknown	unknown	unknown
Address bus width	3	3	3
barrel shifter	NO	NO	NO
boundary scan	NO	NO	NO
maximum clock frequency	20 MHz	20 MHz	20 MHz
External data bus width	16	16	16
Format	FIXED POINT	FIXED POINT	FIXED POINT
Internal bus architecture	MULTIPLE	MULTIPLE	MULTIPLE
JESD-30 code	S-PQCC-J44	S-PQFP-G44	S-PQFP-G44
length	16.5862 mm	10 mm	10 mm
Number of terminals	44	44	44
Maximum operating temperature	70 °C	70 °C	70 °C
Minimum operating temperature	-20 °C	-20 °C	-20 °C
Package body material	PLASTIC/EPOXY	PLASTIC/EPOXY	PLASTIC/EPOXY
encapsulated code	QCCJ	QFP	QFP
Package shape	SQUARE	SQUARE	SQUARE
Package form	CHIP CARRIER	FLATPACK	FLATPACK
Certification status	Not Qualified	Not Qualified	Not Qualified
Maximum seat height	4.57 mm	2.5 mm	2.5 mm
Maximum supply voltage	5.5 V	3.6 V	5.5 V
Minimum supply voltage	4.5 V	3 V	4.5 V
Nominal supply voltage	5 V	3.3 V	5 V
surface mount	YES	YES	YES
technology	CMOS	CMOS	CMOS
Temperature level	COMMERCIAL	COMMERCIAL	COMMERCIAL
Terminal form	J BEND	GULL WING	GULL WING
Terminal pitch	1.27 mm	0.8 mm	0.8 mm
Terminal location	QUAD	QUAD	QUAD
width	16.5862 mm	10 mm	10 mm
uPs/uCs/peripheral integrated circuit type	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER	DIGITAL SIGNAL PROCESSOR, OTHER

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