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Datasheet> All Categories > Analog mixed-signal IC> converter> AD5601BCPZ-RL7
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AD5601BCPZ-RL7

Description
2.7 V to 5.5 V, <100 µA, 8-Bit nanoDAC, SPI Interface in LFCSP and SC70
CategoryAnalog mixed-signal IC    converter   
File Size540KB，21 Pages
ManufacturerADI
Websitehttps://www.analog.com
Environmental Compliance
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AD5601BCPZ-RL7 Overview

2.7 V to 5.5 V, <100 µA, 8-Bit nanoDAC, SPI Interface in LFCSP and SC70

AD5601BCPZ-RL7 Parametric

Parameter NameAttribute value
Brand NameAnalog Devices Inc
Is it lead-free?Contains lead
Is it Rohs certified?conform to
MakerADI
Parts packaging codeSON
package instructionHVSON, SOLCC6,.1,25
Contacts6
Manufacturer packaging codeCP-6-5
Reach Compliance Codecompliant
ECCN codeEAR99
Samacsys DescriptionDigital to Analog Converters - DAC zdzV to 5.5V 8-Bit SPI nanoDAC
Maximum analog output voltage5.5 V
Minimum analog output voltage
Converter typeD/A CONVERTER
Enter bit codeBINARY
Input formatSERIAL
JESD-30 codeR-PDSO-N6
JESD-609 codee3
length3 mm
Maximum linear error (EL)0.1953%
Humidity sensitivity level1
Number of digits8
Number of functions1
Number of terminals6
Maximum operating temperature125 °C
Minimum operating temperature-40 °C
Package body materialPLASTIC/EPOXY
encapsulated codeHVSON
Encapsulate equivalent codeSOLCC6,.1,25
Package shapeRECTANGULAR
Package formSMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius)260
power supply3/5 V
Certification statusNot Qualified
Maximum seat height0.8 mm
Maximum stabilization time10 µs
Nominal settling time (tstl)6 µs
Maximum slew rate0.1 mA
Nominal supply voltage3 V
surface mountYES
technologyCMOS
Temperature levelAUTOMOTIVE
Terminal surfaceMatte Tin (Sn)
Terminal formNO LEAD
Terminal pitch0.65 mm
Terminal locationDUAL
Maximum time at peak reflow temperature30
width2 mm

AD5601BCPZ-RL7 Preview

Data Sheet
FEATURES
2.7 V to 5.5 V, <100 μA, 8-/10-/12-Bit
nanoDAC,
SPI Interface in LFCSP and SC70
AD5601/AD5611/AD5621
FUNCTIONAL BLOCK DIAGRAM
V
DD
GND
POWER-ON
RESET
6-lead SC70 and LFCSP packages
Micropower operation: 100 μA maximum at 5 V
Power-down typically to 0.2 μA at 3 V
2.7 V to 5.5 V power supply
Guaranteed monotonic by design
Power-on reset to 0 V with brownout detection
3 power-down functions
Low power serial interface with Schmitt-triggered inputs
On-chip output buffer amplifier, rail-to-rail operation
SYNC interrupt facility
Minimized zero-code error
AD5601
buffered 8-bit DAC
B version: ±0.5 LSB INL
AD5611
buffered 10-bit DAC
B version: ±0.5 LSB INL
A version: ±4 LSB INL
AD5621
buffered 12-bit DAC
B version: ±1 LSB INL
A version: ±6 LSB INL
AD5601/AD5611/AD5621
DAC
REGISTER
REF(+)
12-/10-/8-BIT
DAC
OUTPUT
BUFFER
V
OUT
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
06853-001
SYNC
SCLK SDIN
Figure 1.
Table 1. Related Devices
Part Number
AD5641
Description
2.7 V to 5.5 V, <100 μA, 14-bit
nanoDAC
in
SC70 and LFCSP packages
APPLICATIONS
Voltage level setting
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
They also provide software-selectable output loads while in
power-down mode. The parts are put into power-down mode
over the serial interface.
The low power consumption of these parts in normal operation
makes them ideally suited to portable battery-operated equip-
ment. The combination of small package and low power makes
these
nanoDAC
devices ideal for level-setting requirements,
such as generating bias or control voltages in space-constrained
and power-sensitive applications.
GENERAL DESCRIPTION
The
AD5601/AD5611/AD5621,
members of the
nanoDAC®
family, are single, 8-/10-/12-bit, buffered voltage output DACs
that operate from a single 2.7 V to 5.5 V supply, consuming
typically 75 μA at 5 V. The parts come in tiny LFCSP and SC70
packages. Their on-chip precision output amplifier allows rail-
to-rail output swing to be achieved. The
AD5601/AD5611/
AD5621
utilize a versatile 3-wire serial interface that operates at
clock rates up to 30 MHz and is compatible with SPI, QSPI™,
MICROWIRE™, and DSP interface standards.
The reference for the
AD5601/AD5611/AD5621
is derived
from the power supply inputs and, therefore, gives the widest
dynamic output range. The parts incorporate a power-on reset
circuit, which ensures that the DAC output powers up to 0 V
and remains there until a valid write to the device takes place.
The
AD5601/AD5611/AD5621
contain a power-down feature
that reduces current consumption to typically 0.2 μA at 3 V.
PRODUCT HIGHLIGHTS
1.
2.
Available in 6-lead LFCSP and SC70 packages.
Low power, single-supply operation. The
AD5601/
AD5611/AD5621
operate from a single 2.7 V to 5.5 V
supply with a maximum current consumption of 100 μA,
making them ideal for battery-powered applications.
The on-chip output buffer amplifier allows the output of
the DAC to swing rail-to-rail with a typical slew rate of
0.5 V/μs.
Reference is derived from the power supply.
High speed serial interface with clock speeds up to
30 MHz. Designed for very low power consumption.
The interface powers up only during a write cycle.
Power-down capability. When powered down, the DAC
typically consumes 0.2 μA at 3 V. Power-on reset with
brownout detection.
3.
4.
5.
6.
Rev. H
Document Feedback
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2005–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
AD5601/AD5611/AD5621
TABLE OF CONTENTS
Features .............................................................................................. 1
 
Applications ....................................................................................... 1
 
General Description ......................................................................... 1
 
Functional Block Diagram .............................................................. 1
 
Product Highlights ........................................................................... 1
 
Revision History ............................................................................... 2
 
Specifications..................................................................................... 3
 
Timing Characteristics ................................................................ 4
 
Absolute Maximum Ratings............................................................ 5
 
ESD Caution .................................................................................. 5
 
Pin Configurations and Function Descriptions ........................... 6
 
Typical Performance Characteristics ............................................. 7
 
Terminology .................................................................................... 13
 
Theory of Operation ...................................................................... 14
 
DAC Section ................................................................................ 14
 
Resistor String ............................................................................. 14
 
Data Sheet
Output Amplifier........................................................................ 14
 
Serial Interface ............................................................................ 14
 
Input Shift Register .................................................................... 14
 
SYNC Interrupt .......................................................................... 14
 
Power-On Reset .......................................................................... 16
 
Power-Down Modes .................................................................. 16
 
Microprocessor Interfacing ....................................................... 16
 
Applications Information .............................................................. 18
 
Choosing a Reference as Power Supply for the
AD5601/AD5611/AD5621 ....................................................... 18
 
Bipolar Operation Using the AD5601/AD5611/AD5621 ..... 18
 
Using the AD5601/AD5611/AD5621 with a Galvanically
Isolated Interface ........................................................................ 19
 
Power Supply Bypassing and Grounding ................................ 19
 
Outline Dimensions ....................................................................... 20
 
Ordering Guide .......................................................................... 21
 
REVISION HISTORY
2/16—Rev. G to Rev. H
Changes to Noise Parameter, Table 2 ............................................. 3
Changes to Serial Interface Section .............................................. 14
6/13—Rev. F to Rev. G
Change to Ordering Guide ............................................................ 21
2/12—Rev. E to Rev. F
Added 6-Lead LFCSP ......................................................... Universal
Changes to Features Section, General Description Section,
Table 1, and Product Highlights Section ....................................... 1
Changes to Table 4 ............................................................................ 5
Added Figure 4; Renumbered Sequentially .................................. 6
Changes to Table 5 ............................................................................ 6
Changes to Choosing a Reference as Power Supply for the
AD5601/AD5611/AD5621 Section .............................................. 18
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 21
7/10—Rev. D to Rev. E
Changes to Figure 1 .......................................................................... 1
5/08—Rev. C to Rev. D
Changes to General Description Section ...................................... 1
Changes to Table 2 ............................................................................ 3
Changes to Choosing a Reference as Power Supply for the
AD5601/AD5611/AD5621 Section .............................................. 18
Changes to Ordering Guide .......................................................... 20
12/07—Rev. B to Rev. C
Changes to Features ..........................................................................1
Changes to Table 2.............................................................................3
Changes to AD5601/AD5611/AD5621 to ADSP-2101
Interface Section ............................................................................. 16
Updated Outline Dimensions ....................................................... 20
Changes to Ordering Guide .......................................................... 20
7/05—Rev. A to Rev. B
Changes to Figure 48...................................................................... 17
Changes to Galvanically Isolated Interface Section ................... 19
Changes to Figure 52...................................................................... 19
3/05—Rev. 0 to Rev. A
Changes to Timing Characteristics .................................................4
Changes to Absolute Maximum Ratings ........................................5
Changes to Full Scale Error Section ................................................7
Changes to Figure 20...................................................................... 10
Changes to Theory of Operation.................................................. 14
Changes to Power Down Modes .................................................. 15
1/05—Revision 0: Initial Version
Rev. H | Page 2 of 21
Data Sheet
SPECIFICATIONS
AD5601/AD5611/AD5621
V
DD
= 2.7 V to 5.5 V; R
L
= 2 kΩ to GND; C
L
= 200 pF to GND; all specifications T
MIN
to T
MAX
, unless otherwise noted. Temperature range
for A/B grades is −40°C to +125°C, typical at 25°C.
Table 2.
Parameter
STATIC PERFORMANCE
AD5601
Resolution
Relative Accuracy
1
(INL)
Differential Nonlinearity (DNL)
AD5611
Resolution
Relative Accuracy
1
(INL)
Differential Nonlinearity (DNL)
AD5621
Resolution
Relative Accuracy
1
(INL)
Differential Nonlinearity (DNL)
Zero-Code Error
Full-Scale Error
Offset Error
Gain Error
Zero-Code Error Drift
Gain Temperature Coefficient
OUTPUT CHARACTERISTICS
2
Output Voltage Range
Output Voltage Settling Time
Slew Rate
Capacitive Load Stability
Output Noise Spectral Density
Noise
Digital-to-Analog Glitch Impulse
Digital Feedthrough
Short-Circuit Current
DC Output Impedance
LOGIC INPUTS
Input Current
3
Input High Voltage, V
INH
Input Low Voltage, V
INL
Pin Input Capacitance
3
Min
A Grade
Typ
Max
Min
B Grade
Typ
Max
Unit
Test Conditions/Comments
8
±0.5
±0.5
10
±4
±0.5
12
±6
±0.5
10
±10
±0.037
±1
±0.5
10
±10
±0.037
±0.5
±0.5
Bits
LSB
LSB
Bits
LSB
LSB
Bits
LSB
LSB
mV
mV
mV
%FSR
μV/°C
ppm
FSR/°C
Guaranteed monotonic by design
Guaranteed monotonic by design
0.5
±0.5
±0.063
±0.0004
5.0
2.0
0.5
±0.5
±0.063
±0.0004
5.0
2.0
Guaranteed monotonic by design
All 0s loaded to DAC register
All 1s loaded to DAC register
0
6
0.5
470
1000
120
2
5
0.2
15
0.5
V
DD
10
0
6
0.5
470
1000
120
2
5
0.2
15
0.5
V
DD
10
V
μs
V/μs
pF
pF
nV/Hz
μV p-p
nV-s
nV-s
mA
Ω
Code ¼ scale to ¾ scale
R
L
= ∞
R
L
= 2 kΩ
DAC code = midscale,1 kHz
DAC code = midscale,
0.1 Hz to 10 Hz bandwidth
1 LSB change around major carry
V
DD
= 3 V/5 V
±2
1.8
1.4
0.8
0.6
3
1.8
1.4
±2
0.8
0.6
μA
V
V
V
V
pF
V
DD
= 4.7 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
V
DD
= 4.7 V to 5.5 V
V
DD
= 2.7 V to 3.6 V
Rev. H | Page 3 of 21
AD5601/AD5611/AD5621
Parameter
POWER REQUIREMENTS
V
DD
I
DD
for Normal Mode
V
DD
= ±4.5 V to ±5.5 V
V
DD
= ±2.7 V to ±3.6 V
I
DD
for All Power-Down Modes
V
DD
= ±4.5 V to ±5.5 V
V
DD
= ±2.7 V to ±3.6 V
POWER EFFICIENCY
I
OUT
/I
DD
1
2
Data Sheet
A Grade
Typ
Max
5.5
Min
2.7
B Grade
Typ
Max
5.5
Unit
V
Test Conditions/Comments
All digital inputs at 0 V or V
DD
DAC active and excluding load
current
V
IH
= V
DD
and V
IL
= GND
V
IH
= V
DD
and V
IL
= GND
V
IH
= V
DD
and V
IL
= GND
V
IH
= V
DD
and V
IL
= GND
V
IH
= V
DD
and V
IL
= GND
I
LOAD
= 2 mA and V
DD
= ±5 V
Min
2.7
75
60
0.5
0.2
96
100
90
75
60
0.5
0.2
96
100
90
μA
μA
μA
μA
%
Linearity calculated using a reduced code range: AD5621 from Code 64 to Code 4032; AD5611 from Code 16 to Code 1008; AD5601 from Code 4 to Code 252.
Guaranteed by design and characterization, not production tested.
3
Total current flowing into all pins.
TIMING CHARACTERISTICS
V
DD
= 2.7 V to 5.5 V; all specifications T
MIN
to T
MAX
, unless otherwise noted. See Figure 2.
Table 3.
Parameter
t
12
t
2
t
3
t
4
t
5
t
6
t
7
t
8
t
9
1
2
Limit
1
33
5
5
10
5
4.5
0
20
13
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
Test Conditions/Comments
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge setup time
Data setup time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
SYNC rising edge to next SCLK falling edge ignored
All input signals are specified with tr = tf = 1 ns/V (10% to 90% of V
DD
) and timed from a voltage level of (V
IL
+ V
IH
)/2.
Maximum SCLK frequency is 30 MHz.
t
4
SCLK
t
2
t
3
t
1
t
9
t
8
t
7
t
6
06853-002
SYNC
t
5
SDIN
D15
D14
D2
D1
D0
D15
D14
Figure 2. Timing Diagram
Rev. H | Page 4 of 21
Data Sheet
ABSOLUTE MAXIMUM RATINGS
T
A
= 25°C, unless otherwise noted.
Table 4.
Parameter
V
DD
to GND
Digital Input Voltage to GND
V
OUT
to GND
Operating Temperature Range
Industrial (A/B Grades)
Storage Temperature Range
Maximum Junction Temperature
SC70 Package
θ
JA
Thermal Impedance
θ
JC
Thermal Impedance
LFCSP Package
θ
JA
Thermal Impedance
Lead Temperature, Soldering
Vapor Phase (60 sec)
Infrared (15 sec)
ESD (Human Body Model)
Rating
−0.3 V to +7.0 V
−0.3 V to V
DD
+ 0.3 V
−0.3 V to V
DD
+ 0.3 V
−40°C to +125°C
−65°C to +160°C
150°C
433.34°C/W
149.47°C/W
95°C/W
215°C
220°C
2.0 kV
AD5601/AD5611/AD5621
Stresses at or above those listed under Absolute Maximum
Ratings may cause permanent damage to the product. This is a
stress rating only; functional operation of the product at these
or any other conditions above those indicated in the operational
section of this specification is not implied. Operation beyond
the maximum operating conditions for extended periods may
affect product reliability.
ESD CAUTION
Rev. H | Page 5 of 21
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AD5601BCPZ-RL7 Related Products

AD5601BCPZ-RL7 AD5611BKSZ-REEL7 AD5611ACPZ-RL7
Description 2.7 V to 5.5 V, <100 µA, 8-Bit nanoDAC, SPI Interface in LFCSP and SC70 2.7 V to 5.5 V, <100 µA, 10-Bit nanoDAC, SPI Interface in LFCSP and SC70 2.7 V to 5.5 V, <100 µA, 10-Bit nanoDAC, SPI Interface in LFCSP and SC70
Brand Name Analog Devices Inc Analog Devices Inc Analog Devices Inc
Is it lead-free? Contains lead Contains lead Contains lead
Is it Rohs certified? conform to conform to conform to
Maker ADI ADI ADI
Parts packaging code SON TSSOP SON
package instruction HVSON, SOLCC6,.1,25 TSSOP, TSSOP6,.08 HVSON, SOLCC6,.1,25
Contacts 6 6 6
Manufacturer packaging code CP-6-5 KS-6 CP-6-5
Reach Compliance Code compliant compliant compliant
ECCN code EAR99 EAR99 EAR99
Maximum analog output voltage 5.5 V 5.5 V 5.5 V
Converter type D/A CONVERTER D/A CONVERTER D/A CONVERTER
Enter bit code BINARY BINARY BINARY
Input format SERIAL SERIAL SERIAL
JESD-30 code R-PDSO-N6 R-PDSO-G6 R-PDSO-N6
JESD-609 code e3 e4 e3
length 3 mm 2 mm 3 mm
Maximum linear error (EL) 0.1953% 0.0488% 0.3906%
Humidity sensitivity level 1 1 1
Number of digits 8 10 10
Number of functions 1 1 1
Number of terminals 6 6 6
Maximum operating temperature 125 °C 125 °C 125 °C
Minimum operating temperature -40 °C -40 °C -40 °C
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code HVSON TSSOP HVSON
Encapsulate equivalent code SOLCC6,.1,25 TSSOP6,.08 SOLCC6,.1,25
Package shape RECTANGULAR RECTANGULAR RECTANGULAR
Package form SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE SMALL OUTLINE, THIN PROFILE, SHRINK PITCH SMALL OUTLINE, HEAT SINK/SLUG, VERY THIN PROFILE
Peak Reflow Temperature (Celsius) 260 260 260
power supply 3/5 V 3/5 V 3/5 V
Certification status Not Qualified Not Qualified Not Qualified
Maximum seat height 0.8 mm 1.1 mm 0.8 mm
Maximum stabilization time 10 µs 10 µs 10 µs
Nominal settling time (tstl) 6 µs 6 µs 6 µs
Maximum slew rate 0.1 mA 0.1 mA 0.1 mA
Nominal supply voltage 3 V 5 V 3 V
surface mount YES YES YES
technology CMOS CMOS CMOS
Temperature level AUTOMOTIVE AUTOMOTIVE AUTOMOTIVE
Terminal surface Matte Tin (Sn) Nickel/Palladium/Gold (Ni/Pd/Au) Matte Tin (Sn)
Terminal form NO LEAD GULL WING NO LEAD
Terminal pitch 0.65 mm 0.65 mm 0.65 mm
Terminal location DUAL DUAL DUAL
Maximum time at peak reflow temperature 30 40 30
width 2 mm 1.25 mm 2 mm

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