Data Sheet
FEATURES
Single 18-bit DAC, ±0.5 LSB INL
7.5 nV/√Hz noise spectral density
0.05 LSB long-term linearity stability
<0.05 ppm/°C temperature drift
1 µs settling time
1.4 nV-sec glitch impulse
Operating temperature range: −40°C to +125°C
20-lead TSSOP package
Wide power supply range of up to ±16.5 V
35 MHz Schmitt triggered digital interface
1.8 V compatible digital interface
True 18-Bit, Voltage Output DAC
±0.5 LSB INL, ±0.5 LSB DNL
AD5781
FUNCTIONAL BLOCK DIAGRAM
V
CC
V
DD
V
REFPF
V
REFPS
6.8kΩ 6.8kΩ
R1
INPUT
SHIFT
REGISTER
AND
CONTROL
LOGIC
18
18
R
FB
R
FB
INV
DAC
REG
18-BIT
DAC
V
OUT
IOV
CC
SDIN
SCLK
SYNC
SDO
LDAC
CLR
RESET
AD5781
A1
6kΩ
POWER-ON-RESET
AND CLEAR LOGIC
09092-001
APPLICATIONS
Medical instrumentation
Test and measurement
Industrial control
Scientific and aerospace instrumentation
Data acquisition systems
Digital gain and offset adjustment
Power supply control
DGND
V
SS
AGND
V
REFNF
V
REFNS
Figure 1.
Table 1. Complementary Devices
Part No.
AD8675
AD8676
ADA4898-1
Description
Ultraprecision, 36 V, 2.8 nV/√Hz rail-to-rail
output op amp
Ultraprecision, 36 V, 2.8 nV/√Hz dual rail-to-
rail output op amp
High voltage, low noise, low distortion, unity
gain stable, high speed op amp
Table 2. Related Devices
Part No.
AD5791
AD5541A/AD5542A
Description
20-bit, 1 ppm accurate DAC
16-bit, 1 LSB accurate 5 V DAC
GENERAL DESCRIPTION
The
AD5781
1
is a single 18-bit, unbuffered voltage output DAC
that operates from a bipolar supply of up to 33 V. The
AD5781
accepts a positive reference input range of 5 V to V
DD
− 2.5 V and
a negative reference input range of V
SS
+ 2.5 V to 0 V. The
AD5781
offers a relative accuracy specification of ±0.5 LSB
maximum, and operation is guaranteed monotonic with a ±0.5
LSB DNL maximum specification.
The part uses a versatile 3-wire serial interface that operates at
clock rates of up to 35 MHz and is compatible with standard
SPI, QSPI™, MICROWIRE™, and DSP interface standards. The
part incorporates a power-on reset circuit that ensures that the
DAC output powers up to 0 V and in a known output impedance
state and remains in this state until a valid write to the device
takes place. The part provides an output clamp feature that
places the output in a defined load state.
1
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
True 18-Bit Accuracy.
Wide Power Supply Range of Up to ±16.5 V.
−40°C to +125°C Operating Temperature Range.
Low 7.5 nV/√Hz Noise.
Low 0.05 ppm/°C Temperature Drift.
Protected by U.S. Patent No 7884747, and other patents are pending.
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Rev. D
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AD5781* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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REFERENCE DESIGNS
•
CN0177
EVALUATION KITS
•
AD5781 Evaluation Board
REFERENCE MATERIALS
Solutions Bulletins & Brochures
•
Digital to Analog Converters ICs Solutions Bulletin
DOCUMENTATION
Data Sheet
•
AD5781-DSCC: Military Data Sheet
•
AD5781-EP: Enhanced Product Data Sheet
•
AD5781: True 18-Bit, Voltage Output DAC ±0.5 LSB INL,
±0.5 LSB DNL Data Sheet
User Guides
•
AD5781/AD5791 Quick Start Guide
•
UG-184: Evaluation Board for a 18-Bit Serial Input, Voltage
Output DAC
DESIGN RESOURCES
•
AD5781 Material Declaration
•
PCN-PDN Information
•
Quality And Reliability
•
Symbols and Footprints
DISCUSSIONS
View all AD5781 EngineerZone Discussions.
SOFTWARE AND SYSTEMS REQUIREMENTS
•
AD5780 - Microcontroller No-OS Driver
•
AD5781 - No-OS Driver for Microchip Microcontroller
Platforms
•
AD5781 - No-OS Driver for Renesas Microcontroller
Platforms
•
AD5781 Pmod Xilinx FPGA Reference Design
•
AD5781 FMC-SDP Interposer & Evaluation Board / Xilinx
KC705 Reference Design
•
BeMicro FPGA Project for AD5781 with Nios driver
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AD5781
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Description .............................. 8
Typical Performance Characteristics ............................................. 9
Terminology .................................................................................... 17
Theory of Operation ...................................................................... 19
Data Sheet
DAC Architecture....................................................................... 19
Hardware Control Pins .............................................................. 20
On-Chip Registers ...................................................................... 21
AD5781 Features ............................................................................ 24
Power-On to 0 V ......................................................................... 24
Configuring the AD5781 .......................................................... 24
DAC Output State ...................................................................... 24
Linearity Compensation ............................................................ 24
Output Amplifier Configuration.............................................. 24
Applications Information .............................................................. 26
Typical Operating Circuit ......................................................... 26
Evaluation Board ........................................................................ 26
Outline Dimensions ....................................................................... 27
Ordering Guide .......................................................................... 27
REVISION HISTORY
7/13—Rev. C to Rev. D
Changes to t
1
Test Conditions/Comments and Endnote 2 ......... 5
Deleted Figure 4 ................................................................................ 7
Deleted Daisy-Chain Operation Section ..................................... 20
11/11—Rev. B to Rev. C
Added Figure 48; Renumbered Sequentially .............................. 17
Change to Ideal Transfer Function Equation.............................. 22
9/11—Rev. A to Rev. B
Added Patent Note ........................................................................... 1
Changes to Table 3 ............................................................................ 3
Changes to OPGND Description, Table 12 ................................ 23
8/11—Rev. 0 to Rev. A
Change to Features Section ..............................................................1
Changes to Specifications Section ...................................................3
Deleted t
14
Parameter from Timing Specifications Section,
Table 4 .................................................................................................5
Changes to Figure 2 and Figure 3 ....................................................6
Changes to Figure 4 ...........................................................................7
Replaced Figure 42 and Figure 43 ................................................ 16
Added New Figure 44, Figure 45, and Figure 46, Renumbered
Sequentially ..................................................................................... 16
7/10—Revision 0: Initial Version
Rev. D | Page 2 of 28
Data Sheet
SPECIFICATIONS
AD5781
V
DD
= +12.5 V to +16.5 V, V
SS
= −16.5 V to −12.5 V, V
REFP
= +10 V, V
REFN
= −10 V, V
CC
= +2.7 V to +5.5 V, IOV
CC
= +1.71 V to +5.5 V,
R
L
= unloaded, C
L
= unloaded, T
MIN
to T
MAX
, unless otherwise noted.
Table 3.
Parameter
STATIC PERFORMANCE
2
Resolution
Integral Nonlinearity Error (Relative
Accuracy)
Min
18
−0.5
−0.5
−1
−4
−0.5
−0.5
−1
A, B Version
1
Typ
Max
Unit
Bits
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
LSB
ppm FSR/°C
LSB
LSB
LSB
LSB
LSB
LSB
ppm FSR/°C
ppm FSR
ppm FSR
ppm FSR
ppm FSR/°C
%
V
V/µs
µs
µs
nV/√Hz
nV/√Hz
nV/√Hz
µV p-p
Test Conditions/Comments
±0.25
±0.25
±0.5
±2
±0.25
±0.25
±0.5
0.04
0.05
0.03
±0.25
±0.062
±0.2
±0.25
±0.062
±0.2
±0.02
±0.025
±0.38
±0.19
±0.025
±0.38
±0.19
±0.04
±0.3
±0.4
±0.4
±0.04
0.01
+0.5
+0.5
+1
+4
+0.5
+0.5
+1
B version, V
REFP
= +10 V, V
REFN
= −10 V
B version, V
REFP
= +10 V, V
REFN
= 0 V
3
B version, V
REFP
= +5 V, V
REFN
= 0 V
3
A version
4
V
REFP
= +10 V, V
REFN
= −10 V
V
REFP
= +10 V, V
REFN
= 0 V
3
V
REFP
= +5 V, V
REFN
= 0 V
3
After 500 hours at T
A
= 125°C
After 1000 hours at T
A
= 125°C
After 1000 hours t T
A
= 100°C
V
REFP
= +10 V, V
REFN
= −10 V
3
V
REFP
= +10 V, V
REFN
= 0 V
3
V
REFP
= +5 V, V
REFN
= 0 V
3
V
REFP
= +10 V, V
REFN
= −10 V
3
,
T
A
= 0°C to 105°C
V
REFP
= 10 V, V
REFN
= 0 V
3
, T
A
= 0°C to 105°C
V
REFP
= 5 V, V
REFN
= 0 V
3
, T
A
= 0°C to 105°C
V
REFP
= +10 V, V
REFN
= −10 V
3
V
REFP
= +10 V, V
REFN
= 0 V
3
V
REFP
= +5 V, V
REFN
= 0 V
3
V
REFP
= +10 V, V
REFN
= −10 V
3
,
T
A
= 0°C to 105°C
V
REFP
= 10 V, V
REFN
= 0 V
3
, T
A
= 0°C to 105°C
V
REFP
= 5 V, V
REFN
= 0 V
3
, T
A
= 0°C to 105°C
V
REFP
= +10 V, V
REFN
= −10 V
3
V
REFP
= +10 V, V
REFN
= 0 V
3
V
REFP
= +5 V, V
REFN
= 0 V
3
Differential Nonlinearity Error
Linearity Error Long-Term Stability
5
Full-Scale Error
−1.75
−2.75
−5.25
−1
−1
−1.5
+1.75
+2.75
+5.25
+1
+1
+1.5
+1.75
+2.5
+5.25
+1
+1
+1.5
+6
+10
+20
Full-Scale Error Temperature Coefficient
3
Zero-Scale Error
−1.75
−2.5
−5.25
−1
−1
−1.5
Zero-Scale Error Temperature Coefficient
3
Gain Error
−6
−10
−20
Gain Error Temperature Coefficient
3
R1, R
FB
Matching
OUTPUT CHARACTERISTICS
3
Output Voltage Range
Output Slew Rate
Output Voltage Settling Time
V
REFN
50
1
1
7.5
7.5
7.5
1.1
V
REFP
Output Noise Spectral Density
Output Voltage Noise
Unbuffered output, 10 MΩ||20 pF load
10 V step to 0.02%, using
AD845
buffer in unity-gain mode
125 code step to ±1 LSB
6
at 1 kHz, DAC code = midscale
at 10 kHz, DAC code = midscale
at 100 kHz, DAC code = midscale
DAC code = midscale, 0.1 Hz to
10 Hz bandwidth
7
Rev. D | Page 3 of 28
AD5781
Parameter
Midscale Glitch Impulse
Min
A, B Version
1
Typ
Max
3.1
1.7
1.4
9.1
3.6
1.9
45
0.4
3.4
6
100
97
5
V
SS
+ 2.5 V
5
V
DD
− 2.5 V
0
6.6
15
−1
0.7 × IOV
CC
5
0.4
IOV
CC
− 0.5 V
±1
3
7.5
V
DD
− 33
2.7
1.71
4.2
4
600
52
±0.6
±0.6
95
95
V
SS
+ 33
−2.5
5.5
5.5
5.2
4.9
900
140
µA
pF
+1
0.3 × IOV
CC
Unit
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
kΩ
kΩ
dB
dB
V
kΩ
pF
µA
V
V
pF
V
Data Sheet
Test Conditions/Comments
V
REFP
= +10 V, V
REFN
= −10 V
V
REFP
= +10 V, V
REFN
= 0 V
V
REFP
= +5 V, V
REFN
= 0 V
V
REFP
= +10 V, V
REFN
= −10 V, see Figure 42
V
REFP
= 10 V, V
REFN
= 0 V, see Figure 43
V
REFP
= 5 V, V
REFN
= 0 V, see Figure 44
On removal of output ground clamp
MSB Segment Glitch Impulse
6
Output Enabled Glitch Impulse
Digital Feedthrough
DC Output Impedance (Normal Mode)
DC Output Impedance (Output
Clamped to Ground)
Spurious Free Dynamic Range
Total Harmonic Distortion
REFERENCE INPUTS
3
V
REFP
Input Range
V
REFN
Input Range
DC Input Impedance
Input Capacitance
LOGIC INPUTS
3
Input Current
8
Input Low Voltage, V
IL
Input High Voltage, V
IH
Pin Capacitance
LOGIC OUTPUT (SDO)
3
Output Low Voltage, V
OL
Output High Voltage, V
OH
High Impedance Leakage Current
High Impedance Output Capacitance
POWER REQUIREMENTS
V
DD
V
SS
V
CC
IOV
CC
I
DD
I
SS
I
CC
IOI
CC
DC Power Supply Rejection Ratio
3, 9
AC Power Supply Rejection Ratio
3
1
2
1 kHz tone, 10 kHz sample rate
1 kHz tone, 10 kHz sample rate
V
REFP
, V
REFN
, code dependent,
typical at midscale code
V
REFP
, V
REFN
IOV
CC
= 1.71 V to 5.5 V
IOV
CC
= 1.71 V to 5.5 V
IOV
CC
= 1.71 V to 5.5 V, sinking 1 mA
IOV
CC
= 1.71 V to 5.5 V, sourcing 1 mA
All digital inputs at DGND or IOV
CC
V
V
V
V
mA
mA
µA
µA
µV/V
µV/V
dB
dB
IOV
CC
≤ V
CC
SDO disabled
V
DD
± 10%, V
SS
= 15 V
V
SS
± 10%, V
DD
= 15 V
V
DD
± 200 mV, 50 Hz/60 Hz, V
SS
= −15 V
V
SS
± 200 mV, 50 Hz/60 Hz, V
DD
= 15 V
Temperature range: −40°C to +125°C, typical conditions: T
A
= 25°C, V
DD
= +15 V, V
SS
= −15 V, V
REFP
= +10 V, V
REFN
= −10 V.
Performance characterized with
AD8676BRZ
voltage reference buffers and
AD8675ARZ
output buffer.
3
Linearity error refers to both INL error and DNL error; either parameter can be expected to drift by the amount specified after the length of time specified.
4
Valid for all voltage reference spans.
5
Guaranteed by design and characterization, not production tested.
6
The
AD5781
is configured in the bias compensation mode with a low-pass RC filter on the output. R = 300 Ω, C = 143 pF (total capacitance seen by the output buffer,
lead capacitance, and so forth).
7
Includes noise contribution from
AD8676BRZ
voltage reference buffers.
8
Current flowing in an individual logic pin.
9
Includes PSRR of
AD8676BRZ
voltage reference buffers.
Rev. D | Page 4 of 28
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