Dual IF Receiver
AD6642
FEATURES
11-bit, 200 MSPS output data rate per channel
Integrated noise shaping requantizer (NSR)
Performance with NSR enabled
SNR: 75.5 dBFS in 40 MHz band to 70 MHz @ 185 MSPS
SNR: 73.7 dBFS in 60 MHz band to 70 MHz @ 185 MSPS
Performance with NSR disabled
SNR: 66.5 dBFS to 70 MHz @ 185 MSPS
SFDR: 83 dBc to 70 MHz @ 185 MSPS
Low power: 0.62 W @ 185 MSPS
1.8 V analog supply operation
1.8 V LVDS (ANSI-644 levels) output
1-to-8 integer clock divider
Internal ADC voltage reference
1.75 V p-p analog input range (programmable to 2.0 V p-p)
Differential analog inputs with 800 MHz bandwidth
95 dB channel isolation/crosstalk
Serial port control
User-configurable built-in self-test (BIST) capability
Energy-saving power-down modes
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND
DRVDD
DRGND
AD6642
VIN+A
VIN–A
VCMA
VIN+B
VIN–B
VCMB
REFERENCE
CLOCK
DIVIDER
SERIAL PORT
PIPELINE
ADC
14
NOISE SHAPING
REQUANTIZER
11
PIPELINE
ADC
14
NOISE SHAPING
REQUANTIZER
11
DATA MULTIPLEXER
AND LVDS DRIVERS
DC0±AB
D0±AB
D10±AB
MODE
SYNC
PDWN
08563-001
SCLK
SDIO
CSB
CLK+ CLK–
Figure 1.
PRODUCT HIGHLIGHTS
1.
2.
Two ADCs are contained in a small, space-saving,
10 mm × 10 mm × 1.4 mm, 144-ball CSP_BGA package.
Pin selectable noise shaping requantizer (NSR) function
that allows for improved SNR within a reduced bandwidth
of up to 60 MHz at 185 MSPS.
LVDS digital output interface configured for low cost
FPGA families.
120 mW per ADC core power consumption.
Operation from a single 1.8 V supply.
Standard serial port interface (SPI) that supports various
product features and functions, such as data formatting
(offset binary or twos complement), NSR, power-down,
test modes, and voltage reference mode.
On-chip integer 1-to-8 input clock divider and multichip
sync function to support a wide range of clocking schemes
and multichannel subsystems.
APPLICATIONS
Communications
Diversity radio and smart antenna (MIMO) systems
Multimode digital receivers (3G)
WCDMA, LTE, CDMA2000
WiMAX, TD-SCDMA
I/Q demodulation systems
General-purpose software radios
3.
4.
5.
6.
7.
Rev. A
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rights of third parties that may result from its use. Specifications subject to change without notice. No
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AD6642* PRODUCT PAGE QUICK LINKS
Last Content Update: 11/29/2017
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TOOLS AND SIMULATIONS
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Visual Analog
EVALUATION KITS
•
AD6642 Evaluation Board
DESIGN RESOURCES
•
AD6642 Material Declaration
•
PCN-PDN Information
•
Quality And Reliability
•
Symbols and Footprints
DOCUMENTATION
Application Notes
•
AN-1142: Techniques for High Speed ADC PCB Layout
•
AN-282: Fundamentals of Sampled Data Systems
•
AN-345: Grounding for Low-and-High-Frequency Circuits
•
AN-501: Aperture Uncertainty and ADC System
Performance
•
AN-586: LVDS Outputs for High Speed A/D Converters
•
AN-737: How ADIsimADC Models an ADC
•
AN-741: Little Known Characteristics of Phase Noise
•
AN-742: Frequency Domain Response of Switched-
Capacitor ADCs
•
AN-756: Sampled Systems and the Effects of Clock Phase
Noise and Jitter
•
AN-807: Multicarrier WCDMA Feasibility
•
AN-808: Multicarrier CDMA2000 Feasibility
•
AN-827: A Resonant Approach to Interfacing Amplifiers to
Switched-Capacitor ADCs
•
AN-835: Understanding High Speed ADC Testing and
Evaluation
•
AN-851: A WiMax Double Downconversion IF Sampling
Receiver Design
•
AN-878: High Speed ADC SPI Control Software
•
AN-905: Visual Analog Converter Evaluation Tool Version
1.0 User Manual
•
AN-935: Designing an ADC Transformer-Coupled Front
End
Data Sheet
•
AD6642: Dual IF Receiver Data Sheet
User Guides
•
UG-232: Evaluating the AD6642/AD6657 Analog-to-
Digital Converters
DISCUSSIONS
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AD6642
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
General Description ......................................................................... 3
Specifications..................................................................................... 4
DC Specifications ......................................................................... 4
AC Specifications.......................................................................... 5
Digital Specifications ................................................................... 6
Switching Specifications .............................................................. 7
Timing Specifications .................................................................. 8
Absolute Maximum Ratings............................................................ 9
Thermal Characteristics .............................................................. 9
ESD Caution.................................................................................. 9
Pin Configuration and Function Descriptions........................... 10
Typical Performance Characteristics ........................................... 12
Equivalent Circuits ......................................................................... 15
Theory of Operation ...................................................................... 16
ADC Architecture ...................................................................... 16
Analog Input Considerations.................................................... 16
Clock Input Considerations ...................................................... 18
Power Dissipation and Standby Mode .................................... 20
Channel/Chip Synchronization................................................ 20
Digital Outputs ........................................................................... 21
Timing ......................................................................................... 21
Noise Shaping Requantizer (NSR) ............................................... 22
22% BW Mode (>40 MHz @ 184.32 MSPS)........................... 22
33% BW Mode (>60 MHz @ 184.32 MSPS)........................... 22
MODE Pin................................................................................... 23
Built-In Self-Test (BIST) and Output Test .................................. 24
Built-In Self-Test (BIST)............................................................ 24
Output Test Modes..................................................................... 24
Serial Port Interface (SPI).............................................................. 25
Configuration Using the SPI..................................................... 25
Hardware Interface..................................................................... 25
Memory Map .................................................................................. 26
Reading the Memory Map Register Table............................... 26
Memory Map Register Table..................................................... 27
Memory Map Register Descriptions........................................ 29
Applications Information .............................................................. 30
Design Guidelines ...................................................................... 30
Outline Dimensions ....................................................................... 31
Ordering Guide .......................................................................... 31
REVISION HISTORY
7/10—Rev. 0 to Rev. A
Changes to ADC Architecture Section........................................ 16
Changes to Figure 34 and Figure 35............................................. 18
Changes to Timing Section and Data Clock Output (DCO)
Section.............................................................................................. 21
Changes to 22% BW Mode (>40 MHz @ 184.32 MSPS) Section
and 33% BW Mode (>60 MHz @ 184.32 MSPS)
Section
......... 22
Changes to Design Guidelines Section........................................ 30
10/09—Revision 0: Initial Version
Rev. A | Page 2 of 32
AD6642
GENERAL DESCRIPTION
The AD6642 is an 11-bit, 200 MSPS, dual-channel intermediate
frequency (IF) receiver specifically designed to support multi-
antenna systems in telecommunication applications where high
dynamic range performance, low power, and small size are desired.
The device consists of two high performance analog-to-digital
converters (ADCs) and noise shaping requantizer (NSR) digital
blocks. Each ADC consists of a multistage, differential pipelined
architecture with integrated output error correction logic. The
ADC features a wide bandwidth switched-capacitor sampling
network within the first stage of the differential pipeline. An
integrated voltage reference eases design considerations. A duty
cycle stabilizer (DCS) compensates for variations in the ADC
clock duty cycle, allowing the converters to maintain excellent
performance.
Each ADC output is connected internally to an NSR block. The
integrated NSR circuitry allows for improved SNR performance
in a smaller frequency band within the Nyquist bandwidth. The
device supports two different output modes selectable via the
external MODE pin or the SPI.
With the NSR feature enabled, the outputs of the ADCs are
processed such that the AD6642 supports enhanced SNR
performance within a limited portion of the Nyquist bandwidth
while maintaining an 11-bit output resolution. The NSR block
can be programmed to provide a bandwidth of either 22% or
33% of the sample clock. For example, with a sample clock rate
of 185 MSPS, the AD6642 can achieve up to 75.5 dBFS SNR for
a 40 MHz bandwidth in the 22% mode and up to 73.7 dBFS
SNR for a 60 MHz bandwidth in the 33% mode.
With the NSR block disabled, the ADC data is provided directly to
the output with a resolution of 11 bits. The AD6642 can achieve
up to 66.5 dBFS SNR for the entire Nyquist bandwidth when
operated in this mode. This allows the AD6642 to be used in
telecommunication applications such as a digital predistortion
observation path where wider bandwidths are desired.
After digital signal processing, multiplexed output data is
routed into two 11-bit output ports such that the maximum
data rate is 400 Mbps (DDR). These outputs are set at 1.8 V
LVDS and support ANSI-644 levels.
The AD6642 receiver digitizes a wide spectrum of IF frequencies.
Each receiver is designed for simultaneous reception of a separate
antenna. This IF sampling architecture greatly reduces compo-
nent cost and complexity compared with traditional analog
techniques or less integrated digital methods.
Flexible power-down options allow significant power savings.
Programming for device setup and control is accomplished
using a 3-wire SPI-compatible serial interface with numerous
modes to support board-level system testing.
The AD6642 is available in a Pb-free/RoHS compliant, 144-ball,
10 mm × 10 mm chip scale package ball grid array (CSP_BGA)
and is specified over the industrial temperature range of −40°C
to +85°C.
Rev. A | Page 3 of 32
AD6642
SPECIFICATIONS
DC SPECIFICATIONS
AVDD = 1.8 V, DRVDD = 1.8 V, f
S
= 185 MSPS, 1.75 V p-p differential input, VIN = −1.0 dBFS differential input, and default SPI, unless
otherwise noted.
Table 1.
Parameter
RESOLUTION
ACCURACY
No Missing Codes
Offset Error
Gain Error
Differential Nonlinearity (DNL)
1
Integral Nonlinearity (INL)
1
MATCHING CHARACTERISTIC
Offset Error
Gain Error
TEMPERATURE DRIFT
Offset Error
Gain Error
ANALOG INPUT
Input Range
Input Common-Mode Voltage
Input Resistance (Differential)
Input Capacitance
2
POWER SUPPLIES
Supply Voltage
AVDD
DRVDD
Supply Current
I
AVDD1
I
DRVDD1
(1.8 V LVDS)
POWER CONSUMPTION
Sine Wave Input
1
Standby Power
3
Power-Down Power
1
2
Temperature
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Full
Min
11
Typ
Max
Unit
Bits
−4.5
Guaranteed
2
±3
±0.1
±0.2
2.5
±1
2
40
7.4
±7
±0.5
±0.5
8.3
±3
mV
% FSR
LSB
LSB
mV
% FSR
ppm/°C
ppm/°C
−2.4
1.4
1.75
0.9
20
5
2.0
V p-p
V
kΩ
pF
Full
Full
Full
Full
Full
Full
Full
1.7
1.7
1.8
1.8
265
79
619
83
4.5
1.9
1.9
291
89
684
18
V
V
mA
mA
mW
mW
mW
Measured with a 10 MHz, 0 dBFS sine wave, with 100 Ω termination on each LVDS output pair.
Input capacitance refers to the effective capacitance between one differential input pin and AGND.
3
Standby power is measured with a dc input and the CLKx pins inactive (set to AVDD or AGND).
Rev. A | Page 4 of 32
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