Serial Input,
14-Bit/16-Bit DAC
AD7849
FEATURES
14-bit/16-bit multiplying DAC
Guaranteed monotonicity
Output control on power-up and power-down internal or
external control
Versatile serial interface
DAC clears to 0 V in both unipolar and bipolar output ranges
V
REF+
R
16-SEGMENT
SWITCH MATRIX
FUNCTIONAL BLOCK DIAGRAM
V
DD
V
CC
R
R
OFS
A1
R
G1
10-BIT/
12-BIT
DAC
10/
12
A3
G2
RST IN
V
OUT
R
APPLICATIONS
Industrial process controls
PC analog I/O boards
Instrumentation
V
REF–
LOGIC
CIRCUITRY
R
A2
DAC
LATCH
10/
12
INPUT
LATCH
INPUT SHIFT REGISTER/
CONTROL LOGIC
01008-001
4
VOLTAGE
MONITOR
AGND
RST OUT
AD7849
DGND
SDIN SCLK SYNC CLR
BIN/
DCEN SDOUT
LDAC
V
SS
COMP
Figure 1.
GENERAL DESCRIPTION
The
AD7849
is a 14-bit/16-bit serial input multiplying digital-
to-analog converter (DAC). The DAC architecture ensures
excellent differential linearity performance, and monotonicity is
guaranteed to 14 bits for the A grade and to 16 bits for all other
grades over the specified temperature ranges.
During power-up and power-down sequences (when the supply
voltages are changing), the V
OUT
pin is clamped to 0 V via a low
impedance path. To prevent the output of A3 from being shorted to
0 V during this time, Transmission Gate G1 is also opened. These
conditions are maintained until the power supplies stabilize,
and a valid word is written to the DAC register. At this time, G2
opens and G1 closes. Both transmission gates are also externally
controllable via the reset in (RSTIN) control input. For instance, if
the RSTIN input is driven from a battery supervisor chip, then
at power-off or during a brown out, the RSTIN input is driven
low to open G1 and close G2. The DAC must be reloaded, with
RSTIN high, to reenable the output. Conversely, the on-chip
voltage detector output (RSTOUT) is also available to the user
to control other parts of the system.
The AD7849 has a versatile serial interface structure and can be
controlled over three lines to facilitate opto-isolator applications.
SDOUT is the output of the on-chip shift register and can be
used in a daisy-chain fashion to program devices in the multi-
channel system. The daisy-chain enable (DCEN) input controls
this function.
The BIN/COMP pin sets the DAC coding; with BIN/COMP set
to 0, the coding is straight binary; and with BIN/COMP set to 1,
the coding is twos complement. This allows the user to reset the
DAC to 0 V in both the unipolar and bipolar output ranges.
The part is available in a 20-lead PDIP package and a 20-lead SOIC
package.
Rev. C
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responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
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Fax: 781.461.3113 ©1995–2011 Analog Devices, Inc. All rights reserved.
AD7849* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
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DOCUMENTATION
Data Sheet
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AD7849: Serial Input, 14-Bit/16-Bit DAC Data Sheet
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AD7849
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Functional Block Diagram .............................................................. 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Reset Specifications ...................................................................... 4
AC Performance Characteristics ................................................ 5
Timing Characteristics ................................................................ 5
Absolute Maximum Ratings............................................................ 6
ESD Caution.................................................................................. 6
Pin Configuration and Function Descriptions............................. 7
Typical Performance Characteristics ..............................................8
Terminology .................................................................................... 10
Circuit Description......................................................................... 11
Digital-to-Analog Conversion.................................................. 11
Digital Interface.......................................................................... 12
Applying the AD7849 ................................................................ 13
Microprocessor Interfacing....................................................... 15
Applications Information .............................................................. 17
Opto-Isolated Interface ............................................................. 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 19
REVISION HISTORY
3/11—Rev. B to Rev. C
Deleted 20-Lead CERDIP (Q-20) Package and
T Version .............................................................................Universal
Updated Format..................................................................Universal
Deleted AD7849-to-ADSP-2101/ADSP-2102 Interface Section
and Figure 20; Renumbered Sequentially.................................... 12
Rev. C | Page 2 of 20
AD7849
SPECIFICATIONS
V
DD
= 14.25 V to 15.75 V; V
SS
= −14.25 V to −15.75 V; V
CC
= 4.75 V to 5.25 V; V
OUT
loaded with 2 kΩ, 200 pF to 0 V; V
REF+
= 5 V; R
OFS
connected to 0 V; T
A
= T
MIN
to T
MAX
, unless otherwise noted. Temperature range for A, B, C versions is −40°C to +85°C.
Table 1.
Parameter
RESOLUTION
UNIPOLAR OUTPUT
Relative Accuracy at 25°C
T
MIN
to T
MAX
Differential Nonlinearity
Gain Error at 25°C
T
MIN
to T
MAX
Offset Error at 25°C
T
MIN
to T
MAX
Gain Temperature Coefficient
1
Offset Temperature Coefficient
1
BIPOLAR OUTPUT
Relative Accuracy at 25°C
T
MIN
to T
MAX
Differential Nonlinearity
Gain Error at 25°C
T
MIN
to T
MAX
Offset Error at 25°C
T
MIN
to T
MAX
Bipolar Zero Error at 25°C
T
MIN
to T
MAX
Gain Temperature Coefficient
1
Offset Temperature Coefficient
1
Bipolar Zero Temperature
Coefficient1
REFERENCE INPUT
Input Resistance
V
REF+
Range
V
REF−
Range
OUTPUT CHARACTERISTICS
Output Voltage Swing
Resistive Load
Capacitive Load
Output Resistance
Short-Circuit Current
A Version
14
B Version
16
C Version
16
Unit
Bits
Test Conditions/Comments
A version: 1 LSB = 2 (V
REF+
− V
REF−
)/2
14
;
B, C versions: 1 LSB = 2 (V
REF+
− V
REF−
)/2
16
V
REF−
= 0 V, V
OUT
= 0 V to 10 V
±4
±5
±0.25
±1
±4
±1
±6
±2
±2
±6
±16
±0.9
±4
±16
±4
±24
±2
±2
±4
±8
±0.5
±4
±16
±4
±16
±2
±2
LSB typ
LSB max
LSB max
LSB typ
LSB max
LSB typ
LSB max
ppm FSR/
°C typ
ppm FSR/
°C typ
LSB typ
LSB max
LSB max
LSB typ
LSB max
LSB typ
LSB max
LSB typ
LSB max
ppm FSR/
°C typ
ppm FSR/
°C typ
ppm FSR/
°C typ
kΩ min
kΩ max
V
V
All grades guaranteed monotonic
over temperature
V
OUT
load = 10 MΩ
V
REF−
= 5 V, V
OUT
= −10 V to +10 V
±2
±3
±0.25
±1
±4
±0.5
±3
±0.5
±4
±2
±2
±2
±3
±8
±0.9
±4
±16
±2
±12
±2
±12
±2
±2
±2
±2
±4
±0.5
±4
±16
±2
±8
±2
±8
±2
±2
±2
All grades guaranteed monotonic
over temperature
V
OUT
load = 10 MΩ
25
43
V
SS
+ 6 to
V
DD
− 6
V
SS
+ 6 to
V
DD
− 6
V
SS
+ 4 to
V
DD
− 4
2
200
0.3
±25
25
43
V
SS
+ 6 to
V
DD
− 6
V
SS
+ 6 to
V
DD
− 6
V
SS
+ 4 to
V
DD
− 4
2
200
0.3
±25
25
43
V
SS
+ 6 to
V
DD
− 6
V
SS
+ 6 to
V
DD
− 6
V
SS
+ 4 to
V
DD
− 4
2
200
0.3
±25
Resistance from V
REF+
to V
REF−
Typically 34 kΩ
V max
kΩ min
pF max
Ω typ
mA typ
To 0 V
To 0 V
Voltage range: −10 V to +10 V
Rev. C | Page 3 of 20
AD7849
Parameter
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
INH
Input Capacitance, C
IN
DIGITAL OUTPUTS
Output Low Voltage, V
OL
Output High Voltage, V
OH
Floating State Leakage Current
Floating State Output
Capacitance
POWER REQUIREMENTS
2
V
DD
V
SS
V
CC
I
DD
I
SS
I
CC
Power Supply Sensitivity
3
Power Dissipation
1
2
A Version
2.4
0.8
±10
10
0.4
4.0
±10
10
B Version
2.4
0.8
±10
10
0.4
4.0
±10
10
C Version
2.4
0.8
±10
10
0.4
4.0
±10
10
Unit
V min
V max
μA max
pF max
V max
V min
μA max
pF max
Test Conditions/Comments
I
SINK
= 1.6 mA
I
SOURCE
= 400 μA
14.25/15.75
−14.25/−15.75
4.75/5.25
5
5
2.5
0.4
100
14.25/15.75
−14.25/−15.75
4.75/5.25
5
5
2.5
1.5
100
14.25/15.75
−14.25/−15.75
4.75/5.25
5
5
2.5
1.5
100
V min/V max
V min/V max
V min/V max
mA max
mA max
mA max
LSB/V max
mW typ
V
OUT
unloaded, V
INH
= V
DD
– 0.1 V,
V
INL
= 0.1 V
V
OUT
unloaded, V
INH
= V
DD
– 0.1 V,
V
INL
= 0.1 V
V
INH
= V
DD
– 0.1 V, V
INL
= 0.1 V
V
OUT
unloaded
Guaranteed by design and characterization, not production tested.
The AD7849 is functional with power supplies of ±12 V. See the Typical Performance Characteristics section.
3
Sensitivity of gain error, offset error, and bipolar zero error to V
DD
, V
SS
variations.
RESET SPECIFICATIONS
These specifications apply when the device goes into reset mode during power-up or power-down sequence. V
OUT
unloaded.
Table 2.
Parameter
V
A
,
1
Low Threshold Voltage for V
DD
, V
SS
V
B
, High Threshold Voltage for V
DD
, V
SS
V
C
, Low Threshold Voltage for V
CC
V
D
, High Threshold Voltage for V
CC
G2 R
ON
1
All Versions
1.2
0
9.5
6.4
1
0
4
2.5
1
Unit
V max
V typ
V max
V min
V max
V typ
V max
V min
kΩ typ
Test Conditions/Comments
This is the lower V
DD
/V
SS
threshold voltage for the reset function.
Above this, the reset is activated.
This is the higher V
DD
/V
SS
threshold voltage for the reset function.
Below this, the reset is activated. Typically, 8 V.
This is the lower V
CC
threshold voltage for the reset function.
Above this, the reset is activated.
This is the higher V
CC
threshold voltage for the reset function.
Below this, the reset is activated. Typically, 3 V.
On resistance of G2; V
DD
= 2 V; V
SS
= −2 V; I
G2
= 1 mA.
A pull-down resistor (65 kΩ) on V
OUT
maintains 0 V output when V
DD
/V
SS
is below V
A
.
Rev. C | Page 4 of 20
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