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PI6C2952-2FBX

Description
PLL Based Clock Driver, 6C Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, LQFP-32
Categorylogic    logic   
File Size69KB,6 Pages
ManufacturerPericom Semiconductor Corporation (Diodes Incorporated)
Websitehttps://www.diodes.com/
Download Datasheet Parametric Compare View All

PI6C2952-2FBX Overview

PLL Based Clock Driver, 6C Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, LQFP-32

PI6C2952-2FBX Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerPericom Semiconductor Corporation (Diodes Incorporated)
Parts packaging codeQFP
package instructionLQFP, QFP32,.35SQ,32
Contacts32
Reach Compliance Codecompliant
ECCN codeEAR99
series6C
Input adjustmentSTANDARD
JESD-30 codeS-PQFP-G32
JESD-609 codee0
length7 mm
Logic integrated circuit typePLL BASED CLOCK DRIVER
MaximumI(ol)0.02 A
Number of functions1
Number of inverted outputs
Number of terminals32
Actual output times11
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeLQFP
Encapsulate equivalent codeQFP32,.35SQ,32
Package shapeSQUARE
Package formFLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius)240
power supply3.3 V
Prop。Delay @ Nom-Sup0.2 ns
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.55 ns
Maximum seat height1.6 mm
Maximum supply voltage (Vsup)3.465 V
Minimum supply voltage (Vsup)3.135 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationQUAD
Maximum time at peak reflow temperatureNOT SPECIFIED
width7 mm
minfmax180 MHz
GNDO
VCCO
Qb2
Qb3
GNDO
GNDO
Qc0
Qc1
VCCO
24 23 22 21 20 19 18 17
16
25
15
26
27
28
29
30
31
32 1
2 3 4
5
6 7 8
14
GNDO
VCCO
VCCO
Qb1
Qb0
Qa4
Qa3
VCO_Sel
fselc
fselb
fsela
MR/OE
REFCLK
GNDI
FBin
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
1
2109876543212109876543210987654321098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI6C2952
Low Voltage PLL Clock Driver
Features
• ±100ps Cycle-to-Cycle Jitter
• Fully Integrated PLL
• Output Frequency up to 180MHz
• High-Impedance Disabled Outputs
• Compatible with PowerPC, Intel, and High-Performance
RISC Microprocessors
• Configurable Output Frequency
• 32-Pin LQFP Package (FB)
Description
The PI6C2952 is a 3.3V compatible, PLL-based clock driver device
targeted for high-performance clock applications. The device fea-
tures a fully integrated PLL with no external components
required. With output frequencies up to 180MHz and eleven low-
skew outputs, the PI6C2952 is well suited for high-performance
designs. The device employs a fully differential PLL design to
optimize jitter and noise rejection performance.
The PI6C2952 features three banks of individually configurable
outputs. The banks contain 5 outputs, 4 outputs, and 2 outputs. The
internal divide circuitry allows for output frequency ratios of 1:1, 2:1,
3:1, and 3:2:1. The output frequency relationship is controlled by the
fsel frequency control pins. The fsel pins and other inputs are
LVCMOS/LVTTL compatible inputs.
The PI6C2952 uses external feedback to the PLL. This features
allows the device to be used as a “zero delay” buffer. Any of the
eleven outputs can be used as feedback to the PLL. To optimize PLL
stability and jitter performance,the VCO_Sel pin allows for the
choice of two VCO ranges. For board level test, the MR/OE pin
allows a user to force the outputs into high impedance. For system
debug, the PI6C2952’s PLL can be bypassed. When forced to a logic
HIGH, the PL_LEN input routes the signal on the RefClk input
around the PLL directly to the internal dividers. Because the signal
is routed through the dividers, it may take several transitions of the
RefClk to affect a transition on the outputs. This features allows a
designer to single step the design for debug purposes.
The PI6C2952’s outputs are LVCMOS which are optimally designed
to drive terminated transmission lines. For applications using series-
terminated transmission lines, each PI6C2952 output can drive two
lines. This capability provides an effective fanout of 22, more than
enough clocks for most clock tree designs.
Pin Configuration
VCCO
Qa2
Qa1
GNDO
Qa0
VCCI
VCCA
PLL_En
32-Pin
FB
13
12
11
10
9
1
PS8542A
01/30-06

PI6C2952-2FBX Related Products

PI6C2952-2FBX PI6C2952-1FBX PI6C2952-1FBEX PI6C2952FBX PI6C2952-2FBE PI6C2952-2FBEX
Description PLL Based Clock Driver, 6C Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, LQFP-32 PLL Based Clock Driver, 6C Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, LQFP-32 PLL Based Clock Driver, 6C Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, LQFP-32 PLL Based Clock Driver, 6C Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, LQFP-32 PLL Based Clock Driver, 6C Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, LQFP-32 PLL Based Clock Driver, 6C Series, 11 True Output(s), 0 Inverted Output(s), PQFP32, LQFP-32
Is it Rohs certified? incompatible incompatible conform to incompatible conform to conform to
Parts packaging code QFP QFP QFP QFP QFP QFP
package instruction LQFP, QFP32,.35SQ,32 LQFP, QFP32,.35SQ,32 LQFP, LQFP, QFP32,.35SQ,32 LQFP, LQFP,
Contacts 32 32 32 32 32 32
Reach Compliance Code compliant compli compliant compliant compliant compliant
ECCN code EAR99 EAR99 EAR99 EAR99 EAR99 EAR99
series 6C 6C 6C 6C 6C 6C
Input adjustment STANDARD STANDARD STANDARD STANDARD STANDARD STANDARD
JESD-30 code S-PQFP-G32 S-PQFP-G32 S-PQFP-G32 S-PQFP-G32 S-PQFP-G32 S-PQFP-G32
JESD-609 code e0 e0 e3 e0 e3 e3
length 7 mm 7 mm 7 mm 7 mm 7 mm 7 mm
Logic integrated circuit type PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER PLL BASED CLOCK DRIVER
Number of functions 1 1 1 1 1 1
Number of terminals 32 32 32 32 32 32
Actual output times 11 11 11 11 11 11
Maximum operating temperature 70 °C 70 °C 70 °C 70 °C 70 °C 70 °C
Output characteristics 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE 3-STATE
Package body material PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY PLASTIC/EPOXY
encapsulated code LQFP LQFP LQFP LQFP LQFP LQFP
Package shape SQUARE SQUARE SQUARE SQUARE SQUARE SQUARE
Package form FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE FLATPACK, LOW PROFILE
Peak Reflow Temperature (Celsius) 240 240 260 240 260 260
Certification status Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified Not Qualified
Same Edge Skew-Max(tskwd) 0.55 ns 0.55 ns 0.55 ns 0.55 ns 0.55 ns 0.55 ns
Maximum seat height 1.6 mm 1.6 mm 1.6 mm 1.6 mm 1.6 mm 1.6 mm
Maximum supply voltage (Vsup) 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V 3.465 V
Minimum supply voltage (Vsup) 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V 3.135 V
Nominal supply voltage (Vsup) 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V 3.3 V
surface mount YES YES YES YES YES YES
Temperature level COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL COMMERCIAL
Terminal surface Tin/Lead (Sn/Pb) Tin/Lead (Sn/Pb) MATTE TIN Tin/Lead (Sn/Pb) MATTE TIN MATTE TIN
Terminal form GULL WING GULL WING GULL WING GULL WING GULL WING GULL WING
Terminal pitch 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm 0.8 mm
Terminal location QUAD QUAD QUAD QUAD QUAD QUAD
Maximum time at peak reflow temperature NOT SPECIFIED NOT SPECIFIED 40 30 40 40
width 7 mm 7 mm 7 mm 7 mm 7 mm 7 mm
minfmax 180 MHz 180 MHz 180 MHz 180 MHz 180 MHz 180 MHz
Is it lead-free? Contains lead Contains lead Lead free - Lead free Lead free
Maker Pericom Semiconductor Corporation (Diodes Incorporated) - Pericom Semiconductor Corporation (Diodes Incorporated) - Pericom Semiconductor Corporation (Diodes Incorporated) Pericom Semiconductor Corporation (Diodes Incorporated)
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