Am29PDS322D
Data Sheet
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Publication Number
23569
Revision
A
Amendment
+4
Issue Date
August 7, 2002
ADVANCE INFORMATION
Am29PDS322D
32 Megabit (2 M x 16-Bit) CMOS 1.8 Volt-only (1.8 V to 2.2 V)
Simultaneous Read/Write Page-Mode Boot Sector Flash Memory
DISTINCTIVE CHARACTERISTICS
ARCHITECTURAL ADVANTAGES
s
Simultaneous Read/Write operations
— Data can be continuously read from one bank while
executing erase/program functions in other bank.
— Zero latency between read and write operations
s
Page Mode Operation
— 4 word page allows fast asynchronous reads
s
Dual Bank architecture
— One 4 Mbit bank and one 28 Mbit bank
s
SecSi (Secured Silicon) Sector: Extra 64 KByte
sector
—
Factory locked and identifiable:
16 byte Electronic
Serial Number available for factory secure, random
ID; verifiable as factory locked through autoselect
function. ExpressFlash option allows entire sector to
be available for factory-secured data
—
Customer lockable:
Can be read, programmed, or
erased just like other sectors. Once locked, data
cannot be changed
s
Zero Power Operation
— Sophisticated power management circuits reduce
power consumed during inactive periods to nearly
zero.
s
Package options
— 48-ball FBGA
s
Top or bottom boot block
s
Manufactured on 0.23 µm process technology
s
Compatible with JEDEC standards
— Pinout and software compatible with
single-power-supply flash standard
PERFORMANCE CHARACTERISTICS
s
High performance
— Access time as fast 40 ns (100 ns random access
time) at 1.8 V to 2.2 V V
CC
— Random access time of 100 ns at 1.8 V to 2.2 V V
CC
will be required as customers migrate downward in
voltage
s
Ultra low power consumption (typical values)
— 2.5 mA active read current at 1 MHz for initial page
read
— 24 mA active read current at 10 MHz for initial page
read
— 0.5 mA active read current at 10 MHz for intra-page
read
— 1 mA active read current at 20 MHz for intra-page
read
— 200 nA in standby or automatic sleep mode
s
Minimum 1 million write cycles guaranteed per
sector
s
20 year data retention at 125°C
— Reliable operation for the life of the system
SOFTWARE FEATURES
s
Data Management Software (DMS)
— AMD-supplied software manages data programming,
enabling EEPROM emulation
— Eases historical sector erase flash limitations
s
Erase Suspend/Erase Resume
— Suspends erase operations to allow programming in
same bank
s
Data# Polling and Toggle Bits
— Provides a software method of detecting the status of
program or erase cycles
s
Unlock Bypass Program command
— Reduces overall programming time when issuing
multiple program command sequences
HARDWARE FEATURES
s
Any combination of sectors can be erased
s
Ready/Busy# output (RY/BY#)
— Hardware method for detecting program or erase
cycle completion
s
Hardware reset pin (RESET#)
— Hardware method of resetting the internal state
machine to the read mode
s
WP#/ACC input pin
— Write protect (WP#) function allows protection of two
outermost boot sectors, regardless of sector protect
status
— Acceleration (ACC) function accelerates program
timing
— ACC voltage is 8.5 V to 12.5 V
s
Sector protection
— Hardware method of locking a sector, either
in-system or using programming equipment, to
prevent any program or erase operation within that
sector
— Temporary Sector Unprotect allows changing data in
protected sectors in-system
This document contains information on a product under development at Advanced Micro Devices. The information
is intended to help you evaluate this product. AMD reserves the right to change or discontinue work on this proposed
product without notice.
Publication#
23569
Rev:
A
Amendment/+4
Issue Date:
August 7, 2002
Refer to AMD’s Website (www.amd.com) for the latest information.
A D V A N C E
I N F O R M A T I O N
GENERAL DESCRIPTION
The Am29PDS322D is a 32 Mbit, 1.8 V-only Flash
memory organized as 2,097,152 words of 16 bits
each. This device is offered in a 48-ball FBGA pack-
age. The device is designed to be programmed in sys-
tem with standard system 1.8 V V
CC
supply. This
device can also be reprogrammed in standard
EPROM programmers.
The Am29PDS322D offers fast page access time of
40 ns with random access time of 100 ns (at 1.8 V to
2.2 V V
CC
), allowing operation of high-speed micropro-
cessors without wait states. To eliminate bus conten-
tion the device has separate chip enable (CE), write
enable (WE), and output enable (OE) controls. The
page size is 4 words.
The device requires only a
single 1.8 volt power sup-
ply
for both read and write functions. Internally
generated and regulated voltages are provided for the
program and erase operations.
other flash sector, or may permanently lock their own
code there.
DMS (Data Management Software)
allows systems
to easily take advantage of the advanced architecture
of the simultaneous read/write product line by allowing
removal of EEPROM devices. DMS will also allow the
system software to be simplified, as it will perform all
functions necessary to modify data in file structures,
as opposed to single-byte modifications. To write or
update a particular piece of data (a phone number or
configuration data, for example), the user only needs
to state which piece of data is to be updated, and
where the updated data is located in the system. This
i s an a d v a nt a g e c o m p a r e d to s y st e m s w h e r e
user-written software must keep track of the old data
location, status, logical to physical translation of the
data onto the Flash memory device (or memory de-
vices), and more. Using DMS, user-written software
does not need to interface with the Flash memory di-
rectly. Instead, the user's software accesses the Flash
memory by calling one of only six functions. AMD pro-
vides this software to simplify system design and soft-
ware integration efforts.
The device offers complete compatibility with the
JEDEC single-power-supply Flash command set
standard.
Commands are written to the command
register using standard microprocessor write timings.
Reading data out of the device is similar to reading
from other Flash or EPROM devices.
The host system can detect whether a program or
erase operation is complete by using the device
sta-
tus bits:
RY/BY# pin, DQ7 (Data# Polling) and
DQ6/DQ2 (toggle bits). After a program or erase cycle
has been completed, the device automatically returns
to the read mode.
The
sector erase architecture
allows memory sec-
tors to be erased and reprogrammed without affecting
the data contents of other sectors. The device is fully
erased when shipped from the factory.
Hardware data protection
measures include a low
V
CC
detector that automatically inhibits write opera-
tions during power transitions. The
hardware sector
protection
feature disables both program and erase
operations in any combination of the sectors of mem-
ory. This can be achieved in-system or via program-
ming equipment.
The device offers two power-saving features. When
addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly re-
duced in both modes.
Simultaneous Read/Write Operations with
Zero Latency
The Simultaneous Read/Write architecture provides
simultaneous operation
by dividing the memory
space into two banks. The device can improve overall
system performance by allowing a host system to pro-
gram or erase in one bank, then immediately and si-
multaneously read from the other bank, with zero
latency. This releases the system from waiting for the
completion of program or erase operations.
The device is divided as shown in the following table:
Bank 1 Sectors
Quantity
8
7
Size
4 Kwords
56
32 Kwords
4 Mbits total
28 Mbits total
32 Kwords
Bank 2 Sectors
Quantity
Size
Am29PDS322D Features
The
SecSi (Secured Silicon) Sector
is an extra 64
KByte sector capable of being permanently locked by
AMD or customers. The
SecSi Indicator Bit
(DQ7) is
permanently set to a 1 if the part is
factory locked,
and set to a 0 if
customer lockable.
This way, cus-
tomer lockable parts can never be used to replace a
factory locked part.
Factory locked parts provide several options. The
SecSi Sector may store a secure, random 16 byte
ESN (Electronic Serial Number), customer code (pro-
grammed through AMD’s ExpressFlash service), or
both. Customer Lockable parts may utilize the SecSi
Sector as bonus space, reading and writing like any
2
Am29PDS322D
August 7, 2002
A D V A N C E
I N F O R M A T I O N
TABLE OF CONTENTS
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . 4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Special Handling Instructions for FBGA Package .................... 5
Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 7
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . 8
Table 1. Am29PDS322D Device Bus Operations .............................8
Sector Erase Command Sequence ........................................ 24
Erase Suspend/Erase Resume Commands ........................... 24
Figure 6. Erase Operation.............................................................. 25
Am29PDS322D Command Definitions . . . . . . . . 26
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 27
DQ7: Data# Polling ................................................................. 27
Figure 7. Data# Polling Algorithm .................................................. 27
Requirements for Reading Array Data ..................................... 8
Read Mode ............................................................................... 8
Random Read (Non-Page Mode Read) ............................................8
RY/BY#: Ready/Busy#............................................................ 28
DQ6: Toggle Bit I .................................................................... 28
Figure 8. Toggle Bit Algorithm........................................................ 28
Page Mode Read ...................................................................... 9
Table 2. Page Word Mode ................................................................9
Writing Commands/Command Sequences .............................. 9
Accelerated Program Operation ........................................................9
Autoselect Functions .........................................................................9
DQ2: Toggle Bit II ................................................................... 29
Reading Toggle Bits DQ6/DQ2 ............................................... 29
DQ5: Exceeded Timing Limits ................................................ 29
DQ3: Sector Erase Timer ....................................................... 29
Table 11. Write Operation Status ................................................... 30
Absolute Maximum Ratings. . . . . . . . . . . . . . . . . 31
Figure 9. Maximum Negative Overshoot Waveform ...................... 31
Figure 10. Maximum Positive Overshoot Waveform...................... 31
Simultaneous Read/Write Operations with Zero Latency ......... 9
Standby Mode .......................................................................... 9
Automatic Sleep Mode ........................................................... 10
RESET#: Hardware Reset Pin ............................................... 10
Output Disable Mode .............................................................. 10
Table 3. Am29PDS322DT Top Boot Sector Addresses ..................11
Table 4. Am29PDS322DT Top Boot SecSi Sector Address ...........12
Table 5. Am29PDS322DB Bottom Boot Sector Addresses ............12
Table 6. Am29PDS322DB Bottom Boot SecSi Sector Address . . .14
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 31
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure 11. I
CC1
Current vs. Time (Showing Active and Automatic
Sleep Currents) .............................................................................. 33
Figure 12. Typical I
CC1
vs. Frequency ............................................ 33
Test Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure 13. Test Setup.................................................................... 34
Table 12. Test Specifications ......................................................... 34
Autoselect Mode..................................................................... 15
Table 7. Autoselect Codes (High Voltage Method) ........................15
Key to Switching Waveforms. . . . . . . . . . . . . . . . 34
Figure 14. Input Waveforms and Measurement Levels ................. 34
Sector/Sector Block Protection and Unprotection .................. 16
Table 8. Top Boot Sector/Sector Block Addresses for
Protection/Unprotection ...................................................................16
Table 9. Bottom Boot Sector/Sector Block Addresses for
Protection/Unprotection ...................................................................16
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure 15. Conventional Read Operation Timings ......................... 35
Figure 16. Page Mode Read Timings ............................................ 36
Hardware Reset (RESET#) .................................................... 37
Figure 17. Reset Timings ............................................................... 37
Write Protect (WP#) ................................................................ 17
Temporary Sector/Sector Block Unprotect ............................. 17
Figure 1. Temporary Sector Unprotect Operation........................... 17
Figure 2. Temporary Sector Group Unprotect Operation................ 18
Figure 3. In-System Sector Group Protect/Unprotect Algorithms ... 19
Erase and Program Operations .............................................. 38
Figure 18. Program Operation Timings..........................................
Figure 19. Accelerated Program Timing Diagram..........................
Figure 20. Chip/Sector Erase Operation Timings ..........................
Figure 21. Back-to-back Read/Write Cycle Timings ......................
Figure 22. Data# Polling Timings (During Embedded Algorithms).
Figure 23. Toggle Bit Timings (During Embedded Algorithms)......
Figure 24. DQ2 vs. DQ6.................................................................
39
39
40
41
41
42
42
SecSi (Secured Silicon) Sector Flash Memory Region .......... 20
Factory Locked: SecSi Sector Programmed and Protected
at the Factory ..................................................................................20
Hardware Data Protection ...................................................... 20
Low V
CC
Write Inhibit .......................................................................20
Write Pulse “Glitch” Protection ........................................................21
Logical Inhibit ..................................................................................21
Power-Up Write Inhibit ....................................................................21
Temporary Sector Unprotect .................................................. 43
Figure 25. Temporary Sector Group Unprotect Timing Diagram ... 43
Figure 26. Sector Group Protect and Unprotect Timing Diagram .. 44
Alternate CE# Controlled Erase and Program Operations ..... 45
Figure 27. Alternate CE# Controlled Write (Erase/Program)
Operation Timings.......................................................................... 46
Command Definitions . . . . . . . . . . . . . . . . . . . . . 21
Reading Array Data ................................................................ 21
Reset Command ..................................................................... 21
Autoselect Command Sequence ............................................ 21
Enter SecSi Sector/Exit SecSi Sector Command Sequence .. 22
Word Program Command Sequence ..................................... 22
Unlock Bypass Command Sequence ..............................................22
Chip Erase Command Sequence ........................................... 22
Figure 4. Unlock Bypass Algorithm ................................................. 23
Figure 5. Program Operation .......................................................... 23
Erase And Programming Performance. . . . . . . . 47
Latchup Characteristics . . . . . . . . . . . . . . . . . . . . 47
Data Retention. . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . 48
FBD048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
12 x 6 mm package ................................................................ 48
Revision Summary . . . . . . . . . . . . . . . . . . . . . . . . 49
August 7, 2002
Am29PDS322D
3
A D V A N C E
I N F O R M A T I O N
PRODUCT SELECTOR GUIDE
Part Number
Speed Options
Standard Voltage Range: V
CC
= 1.8–2.2 V
10
100
40
100
35
Am29PDS322D
12
120
45
120
40
Max Random Address Access Time (ns)
Max Page Address Access Time (ns)
CE# Access Time (ns)
OE# Access Time (ns)
Note:
See “AC Characteristics” for full specifications.
BLOCK DIAGRAM
V
CC
V
SS
OE#
Mux
Y-Decoder
A0–A20
Upper Bank Address
Upper Bank
Latches and Control Logic
RY/BY#
A0–A20
RESET#
WE#
CE#
WP#/ACC
DQ0–DQ15
A0–A20
STATE
CONTROL
&
COMMAND
REGISTER
Status
X-Decoder
DQ0–DQ15
A0–A20
DQ0–DQ15
Control
DQ0–DQ15
Mux
X-Decoder
Lower Bank
A0–A20
Mux
Lower Bank Address
4
Am29PDS322D
Latches and
Control Logic
Y-Decoder
August 7, 2002
FPGA/CPLD
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