2.1 Ω On Resistance, ±15 V/+12 V/±5 V
iCMOS
Dual SPST Switches
Data Sheet
FEATURES
2.1 Ω on resistance
0.5 Ω maximum on resistance flatness
Up to 250 mA continuous current
Fully specified at +12 V, ±15 V, ±5 V
No V
L
supply required
3 V logic-compatible inputs
Rail-to-rail operation
10-lead MSOP and 10-lead, 3 mm × 3 mm LFCSP packages
ADG1421/ADG1422/ADG1423
FUNCTIONAL BLOCK DIAGRAM
ADG1421
S1
IN1
D1
D2
IN2
S2
08487-001
SWITCHES SHOWN FOR A LOGIC 0 INPUT
Figure 1.
ADG1421
Functional Block Diagram
APPLICATIONS
Automatic test equipment
Data acquisition systems
Relay replacements
Battery-powered systems
Sample-and-hold systems
Audio signal routing
Video signal routing
Communication systems
ADG1422
S1
IN1
D1
D2
IN2
S2
08487-002
08487-003
SWITCHES SHOWN FOR A LOGIC 0 INPUT
Figure 2.
ADG1422
Functional Block Diagram
GENERAL DESCRIPTION
The
ADG1421/ADG1422/ADG1423
contain two independent
single-pole/single-throw (SPST) switches. The
ADG1421
and
ADG1422
differ only in that the digital control logic is inverted.
The
ADG1421
switches are turned on with Logic 1 on the
appropriate control input, and Logic 0 is required for the
ADG1422.
The
ADG1423
has one switch with digital control
logic similar to that of the
ADG1421;
the logic is inverted on
the other switch. The
ADG1423
exhibits break-before-make
switching action for use in multiplexer applications. Each
switch conducts equally well in both directions when on and
has an input signal range that extends to the supplies. In the
off condition, signal levels up to the supplies are blocked.
The
iCMOS®
(industrial CMOS) modular manufacturing process
combines high voltage, complementary metal-oxide semiconductor
(CMOS) and bipolar technologies. It enables the development
of a wide range of high performance analog ICs capable of 33 V
operation in a footprint that no other generation of high voltage
parts has achieved. Unlike analog ICs using conventional CMOS
processes,
iCMOS
components can tolerate high supply voltages
while providing increased performance, dramatically lower
power consumption, and reduced package size.
ADG1423
S1
IN1
D1
D2
IN2
S2
SWITCHES SHOWN FOR A LOGIC 0 INPUT
Figure 3.
ADG1423
Functional Block Diagram
The on resistance profile is very flat over the full analog input
range ensuring excellent linearity and low distortion when
switching audio signals. The
iCMOS
construction ensures
ultralow power dissipation, making the part ideally suited for
portable and battery-powered instruments.
PRODUCT HIGHLIGHTS
1.
2.
3.
4.
5.
2.4 Ω maximum on resistance at 25°C.
Minimum distortion.
3 V logic-compatible digital inputs: V
INH
= 2.0 V, V
INL
= 0.8 V.
No V
L
logic power supply required.
10-lead MSOP and 10-lead, 3 mm × 3 mm LFCSP packages.
Rev. A
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Trademarks and registered trademarks are the property of their respective owners.
ADG1421/ADG1422/ADG1423
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Product Highlights ........................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
±15 V Dual Supply ....................................................................... 3
+12 V Single Supply ..................................................................... 4
±5 V Dual Supply ......................................................................... 5
Data Sheet
Continuous Current per Channel, S or D ..................................6
Absolute Maximum Ratings ............................................................7
Thermal Resistance .......................................................................7
ESD Caution...................................................................................7
Pin Configuration and Function Descriptions..............................8
Typical Performance Characteristics ..............................................9
Test Circuits..................................................................................... 12
Terminology .................................................................................... 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 16
REVISION HISTORY
7/14—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 3
Updated Outline Dimensions ....................................................... 15
10/09—Revision 0: Initial Version
Rev. A | Page 2 of 16
Data Sheet
SPECIFICATIONS
±15 V DUAL SUPPLY
V
DD
= +15 V ± 10%, V
SS
= −15 V ± 10%, GND = 0 V, unless otherwise noted.
Table 1.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, R
ON
On Resistance Match Between Channels, ∆R
ON
On Resistance Flatness, R
FLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, I
S
(Off)
Drain Off Leakage, I
D
(Off)
Channel On Leakage, I
D
, I
S
(On)
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
INL
or I
INH
Digital Input Capacitance, C
IN
DYNAMIC CHARACTERISTICS
1
t
ON
t
OFF
Break-Before-Make Time Delay, t
D
(ADG1423 Only)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
Insertion Loss
C
S
(Off)
C
D
(Off)
C
D
, C
S
(On)
POWER REQUIREMENTS
I
DD
I
DD
I
SS
V
DD
/V
SS
1
ADG1421/ADG1422/ADG1423
25°C
−40°C to
+85°C
−40°C to
+105°C
−40°C to
+125°C
V
DD
to V
SS
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
MHz typ
dB typ
pF typ
pF typ
pF typ
μA typ
μA max
μA typ
μA max
μA typ
μA max
V min/max
Test Conditions/Comments
2.1
2.4
0.02
0.1
0.4
0.5
±0.1
±0.5
±0.1
±0.5
±0.2
±1
2.8
0.12
0.6
2.95
0.124
0.63
3.2
0.13
0.65
V
S
= ±10 V, I
S
= −10 mA; see Figure 23
V
DD
= +13.5 V, V
SS
= −13.5 V
V
S
= ±10 V, I
S
= −10 mA
V
S
= ±10 V, I
S
= −10 mA
V
DD
= +16.5 V, V
SS
= −16.5 V
V
S
= ±10 V, V
D
= ±10 V; see Figure 24
V
S
= ±10 V, V
D
= ±10 V; see Figure 24
V
S
= V
D
= ±10 V; see Figure 25
±2
±2
±2
±9
±9
±9
±75
±75
±75
2.0
0.8
0.005
±0.1
4
115
145
115
145
45
−5
−64
−74
0.016
180
0.12
18
22
86
0.002
1.0
120
190
0.002
1.0
±4.5/±16.5
V
IN
= V
GND
or V
DD
180
165
210
190
30
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 10 V; see Figure 26
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 10 V; see Figure 26
R
L
= 300 Ω, C
L
= 35 pF
V
S1
= V
S2
= 10 V; see Figure 27
V
S
= 0 V, R
S
= 0 Ω, C
L
= 1 nF;
see Figure 28
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
see Figure 29
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
see Figure 30
R
L
= 10 kΩ, 5 V rms, f = 20 Hz to 20 kHz;
see Figure 32
R
L
= 50 Ω, C
L
= 5 pF; see Figure 31
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
see Figure 31
f = 1 MHz; V
S
= 0 V
f = 1 MHz; V
S
= 0 V
f = 1 MHz; V
S
= 0 V
V
DD
= +16.5 V, V
SS
= −16.5 V
Digital inputs = 0 V or V
DD
Digital inputs = 5 V
Digital inputs = 0 V, 5 V, or V
DD
Ground = 0 V
Guaranteed by design, not subject to production test.
Rev. A | Page 3 of 16
ADG1421/ADG1422/ADG1423
+12 V SINGLE SUPPLY
V
DD
= 12 V ± 10%, V
SS
= 0 V, GND = 0 V, unless otherwise noted.
Table 2.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, R
ON
On Resistance Match Between Channels, ∆R
ON
On Resistance Flatness, R
FLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, I
S
(Off )
Drain Off Leakage, I
D
(Off )
Channel On Leakage, I
D
, I
S
(On)
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
INL
or I
INH
Digital Input Capacitance, C
IN
DYNAMIC CHARACTERISTICS
1
t
ON
t
OFF
Break-Before-Make Time Delay, t
D
(ADG1423 Only)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
−3 dB Bandwidth
Insertion Loss
C
S
(Off )
C
D
(Off )
C
D
, C
S
(On)
POWER REQUIREMENTS
I
DD
I
DD
V
DD
1
Data Sheet
25°C
−40°C to
+85°C
−40°C to
+125°C
0 V to V
DD
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
nA max
nA typ
nA max
nA typ
nA max
V min
V max
µA typ
µA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
MHz typ
dB typ
pF typ
pF typ
pF typ
µA typ
µA max
µA typ
µA max
V min/max
Test Conditions/Comments
4
4.6
0.03
0.15
1.2
1.5
±0.05
±0.5
±0.05
±0.5
±0.1
±1
5.5
0.17
1.75
6.2
0.18
1.9
V
S
= 0 V to 10 V, I
S
= −10 mA; see Figure 23
V
DD
= 10.8 V, V
SS
= 0 V
V
S
= 0 V to 10 V, I
S
= −10 mA
V
S
= 0V to 10 V, I
S
= −10 mA
V
DD
= 13.2 V, V
SS
= 0 V
V
S
= 1 V/10 V, V
D
= 10 V/1 V; see Figure 24
V
S
= 1 V/10 V, V
D
= 10 V/1 V; see Figure 24
V
S
= V
D
= 1 V or 10 V; see Figure 25
±2
±2
±2
±75
±75
±75
2.0
0.8
0.005
±0.1
4
180
230
130
165
70
30
−60
−70
140
0.26
31
36
90
0.001
1.0
120
190
5/16.5
V
IN
= V
GND
or V
DD
295
205
340
235
48
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 8 V; see Figure 26
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 8 V; see Figure 26
R
L
= 300 Ω, C
L
= 35 pF
V
S1
= V
S2
= 8 V; see Figure 27
V
S
= 6 V, R
S
= 0 Ω, C
L
= 1 nF;
see Figure 28
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
see Figure 29
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
see Figure 30
R
L
= 50 Ω, C
L
= 5 pF; see Figure 31
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
see Figure 31
f = 1 MHz; V
S
= 6 V
f = 1 MHz; V
S
= 6 V
f = 1 MHz; V
S
= 6 V
V
DD
= 13.2 V
Digital inputs = 0 V or V
DD
Digital inputs = 5 V
Ground = 0 V, V
SS
= 0 V
Guaranteed by design, not subject to production test.
Rev. A | Page 4 of 16
Data Sheet
±5 V DUAL SUPPLY
V
DD
= +5 V ± 10%, V
SS
= −5 V ± 10%, GND = 0 V, unless otherwise noted.
Table 3.
Parameter
ANALOG SWITCH
Analog Signal Range
On Resistance, R
ON
On Resistance Match Between Channels, ∆R
ON
On Resistance Flatness, R
FLAT (ON)
LEAKAGE CURRENTS
Source Off Leakage, I
S
(Off)
Drain Off Leakage, I
D
(Off)
Channel On Leakage, I
D
, I
S
(On)
DIGITAL INPUTS
Input High Voltage, V
INH
Input Low Voltage, V
INL
Input Current, I
INL
or I
INH
Digital Input Capacitance, C
IN
DYNAMIC CHARACTERISTICS
1
t
ON
t
OFF
Break-Before-Make Time Delay, t
D
(ADG1423 Only)
Charge Injection
Off Isolation
Channel-to-Channel Crosstalk
Total Harmonic Distortion + Noise
−3 dB Bandwidth
Insertion Loss
C
S
(Off)
C
D
(Off)
C
D
, C
S
(On)
POWER REQUIREMENTS
I
DD
I
SS
V
DD
/V
SS
1
ADG1421/ADG1422/ADG1423
25°C
−40°C to
+85°C
−40°C to
+125°C
V
DD
to V
SS
Unit
V
Ω typ
Ω max
Ω typ
Ω max
Ω typ
Ω max
nA typ
Test Conditions/Comments
4.5
5.2
0.04
0.18
1.3
1.6
±0.05
±0.5
±0.05
±0.5
±0.1
±1
6.2
0.2
1.85
7
0.21
2
V
S
= ±4.5 V, I
S
= −10 mA; see Figure 23
V
DD
= +4.5 V, V
SS
= −4.5 V
V
S
= ±4.5V; I
S
= −10 mA
V
S
= ±4.5 V, I
S
= −10 mA
V
DD
= +5.5 V, V
SS
= −5.5 V
V
S
= ±4.5 V, V
D
=
∓4.5
V; see Figure 24
V
S
= ±4.5 V, V
D
=
∓4.5
V; see Figure 24
V
S
= V
D
= ±4.5 V; see Figure 25
±2
±2
±2
±75
±75
±75
2.0
0.8
nA max
nA typ
nA max
nA typ
nA max
V min
V max
μA typ
μA max
pF typ
ns typ
ns max
ns typ
ns max
ns typ
ns min
pC typ
dB typ
dB typ
% typ
MHz typ
dB typ
pF typ
pF typ
pF typ
μA typ
μA max
μA typ
μA max
V min/max
0.005
±0.1
4
285
370
220
295
85
82
−60
−70
0.04
150
0.25
25
30
100
0.001
1.0
0.001
1.0
±4.5/±16.5
V
IN
= V
GND
or V
DD
460
350
520
395
45
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 3 V; see Figure 26
R
L
= 300 Ω, C
L
= 35 pF
V
S
= 3 V; see Figure 26
R
L
= 300 Ω, C
L
= 35 pF
V
S1
= V
S2
= 3 V; see Figure 27
V
S
= 0 V, R
S
= 0 Ω, C
L
= 1 nF;
see Figure 28
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
see Figure 29
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
see Figure 30
R
L
= 10 kΩ, 5 V p-p, f = 20 Hz to 20 kHz;
see Figure 32
R
L
= 50 Ω, C
L
= 5 pF; see Figure 31
R
L
= 50 Ω, C
L
= 5 pF, f = 1 MHz;
see Figure 31
V
S
= 0V, f = 1 MHz
V
S
= 0V, f = 1 MHz
V
S
= 0V, f = 1 MHz
V
DD
= 5.5 V, V
SS
= −5.5 V
Digital inputs = 0 V or V
DD
Digital inputs = 0 V or V
DD
Ground = 0 V
Guaranteed by design, not subject to production test.
Rev. A | Page 5 of 16
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