2050 MHz to 3000 MHz Quadrature Modulator with
2500 MHz to 2900 MHz Frac-N PLL and Integrated VCO
Data Sheet
FEATURES
IQ modulator with integrated fractional-N PLL
Output frequency range: 2050 MHz to 3000 MHz
Internal LO frequency range: 2500 MHz to 2900 MHz
Output P1dB: 12.1 dBm @ 2700 MHz
Output IP3: 27.2 dBm @ 2700 MHz
Noise floor: −158.3 dBm/Hz @ 2700 MHz
Baseband bandwidth: 750 MHz (3 dB)
SPI serial interface for PLL programming
Integrated LDOs and LO buffer
Power supply: 5 V/226 mA
40-lead 6 mm × 6 mm LFCSP
ADRF6704
modulator, PLL, and VCO provides for significant board
savings and reduces the BOM and design complexity.
The integrated fractional-N PLL/synthesizer generates a 2× f
LO
input to the IQ modulator. The phase detector together with an
external loop filter is used to control the VCO output. The VCO
output is applied to a quadrature divider. To reduce spurious
components, a sigma-delta (Σ-Δ) modulator controls the
programmable PLL divider.
The IQ modulator has wideband differential I and Q inputs,
which support baseband as well as complex IF architectures.
The single-ended modulator output is designed to drive a
50 Ω load impedance and can be disabled.
The
ADRF6704
is fabricated using an advanced silicon-
germanium BiCMOS process. It is available in a 40-lead,
exposed-paddle, Pb-free, 6 mm × 6 mm LFCSP package.
Performance is specified from −40°C to +85°C. A lead-free
evaluation board is available.
Table 1.
Part No.
ADRF6701
ADRF6702
ADRF6703
ADRF6704
Internal LO Range
750 MHz
1150 MHz
1550 MHz
2150 MHz
2100 MHz
2600 MHz
2500 MHz
2900 MHz
IQ Modulator
±3 dB RF Output Range
400 MHz
1250 MHz
1200 MHz
2400 MHz
1550 MHz
2650 MHz
2050 MHz
3000 MHz
APPLICATIONS
Cellular communications systems
GSM/EDGE, CDMA2000, W-CDMA, TD-SCDMA, LTE
Broadband wireless access systems
Satellite modems
GENERAL DESCRIPTION
The
ADRF6704
provides a quadrature modulator and
synthesizer solution within a small 6 mm × 6 mm footprint
while requiring minimal external components.
The
ADRF6704
is designed for RF outputs from 2050 MHz to
3000 MHz. The low phase noise VCO and high performance
quadrature modulator make the
ADRF6704
suitable for next
generation communication systems requiring high signal
dynamic range and linearity. The integration of the IQ
FUNCTIONAL BLOCK DIAGRAM
VCC7
34
VCC6
29
VCC5
27
VCC4
22
VCC3
17
VCC2
10
VCC1
1
LOSEL
36
LON
37
BUFFER
ADRF6704
DIVIDER
÷2
2:1
MUX
40
9
2
DECL3
DECL2
DECL1
LOP
38
BUFFER
DATA
12
CLK
13
LE
14
SPI
INTERFACE
FRACTION
REG
MODULUS
INTEGER
REG
THIRD-ORDER
FRACTIONAL
INTERPOLATOR
×2
N COUNTER
21 TO 123
MUX
TEMP
SENSOR
4
7
REFIN
6
÷2
÷4
MUXOUT
8
PRESCALER
÷2
CHARGE PUMP
250µA,
500µA (DEFAULT),
750µA,
1000µA
24
5
3
VCO
CORE
18
QP
QN
IN
IP
÷2
0/90
19
32
33
–
PHASE
+ FREQUENCY
DETECTOR
11 15 20 21 23 25 28 30 31 35
39
16
26
08571-001
GND
NOTES
1. NC = NO CONNECT. DO NOT CONNECT TO THIS PIN.
NC
RSET
CP VTUNE ENOP RFOUT
Figure 1.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2011 Analog Devices, Inc. All rights reserved.
ADRF6704* PRODUCT PAGE QUICK LINKS
Last Content Update: 02/23/2017
COMPARABLE PARTS
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DESIGN RESOURCES
•
ADRF6704 Material Declaration
•
PCN-PDN Information
•
Quality And Reliability
•
Symbols and Footprints
EVALUATION KITS
•
ADRF6704 Evaluation Board
DOCUMENTATION
Application Notes
•
AN-1100: Wireless Transmitter IQ Balance and Sideband
Suppression
Data Sheet
•
ADRF6704: 2500 MHz to 2900 MHz Quadrature Modulator
with Integrated Fractional-N PLL and VCO Data Sheet
DISCUSSIONS
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SAMPLE AND BUY
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TECHNICAL SUPPORT
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number.
TOOLS AND SIMULATIONS
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REFERENCE MATERIALS
Press
• Industry’s First Half Watt RF Driver Amplifier with
Dynamically Adjustable Bias and Extended Temperature
Range
Product Selection Guide
•
RF Source Booklet
Technical Articles
•
Integrated Devices Arm Infrastructure Radios
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ADRF6704
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Timing Characteristics ................................................................ 6
Absolute Maximum Ratings............................................................ 7
ESD Caution.................................................................................. 7
Pin Configuration and Function Descriptions............................. 8
Typical Performance Characteristics ........................................... 10
Theory of Operation ...................................................................... 16
PLL + VCO.................................................................................. 16
Basic Connections for Operation............................................. 16
External LO ................................................................................. 16
Loop Filter ................................................................................... 17
DAC-to-IQ Modulator Interfacing .......................................... 18
Adding a Swing-Limiting Resistor ........................................... 18
IQ Filtering .................................................................................. 19
Data Sheet
Baseband Bandwidth ................................................................. 19
Device Programming and Register Sequencing..................... 19
Register Summary .......................................................................... 20
Register Description....................................................................... 21
Register 0—Integer Divide Control (Default: 0x0001C0) .... 21
Register 1—Modulus Divide Control (Default: 0x003001).. 22
Register 2—Fractional Divide Control (Default: 0x001802) ..22
Register 3—Σ-Δ Modulator Dither Control (Default:
0x10000B).................................................................................... 23
Register 4—PLL Charge Pump, PFD, and Reference Path
Control (Default: 0x12A7E4).................................................... 24
Register 5—LO Path and Modulator Control (Default:
0x0000E5).................................................................................... 26
Register 6—VCO Control and VCO Enable (Default:
0x1E2106).................................................................................... 27
Characterization Setups................................................................. 28
Evaluation Board ............................................................................ 30
Evaluation Board Control Software......................................... 30
Outline Dimensions ....................................................................... 35
Ordering Guide .......................................................................... 35
REVISION HISTORY
10/11—Revision 0: Initial Version
Rev. 0 | Page 2 of 36
Data Sheet
SPECIFICATIONS
ADRF6704
V
S
= 5 V; T
A
= 25°C; baseband I/Q amplitude = 1 V p-p differential sine waves in quadrature with a 500 mV dc bias; baseband I/Q
frequency (f
BB
) = 1 MHz; f
PFD
= 38.4 MHz; f
REF
= 153.6 MHz at +4 dBm Re:50 Ω (1 V p-p); 130 kHz loop filter, unless otherwise noted.
Table 2.
Parameter
OPERATING FREQUENCY RANGE
RF OUTPUT = 2500 MHz
Nominal Output Power
IQ Modulator Voltage Gain
OP1dB
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
RF OUTPUT = 2700 MHz
Nominal Output Power
IQ Modulator Voltage Gain
OP1dB
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
RF OUTPUT = 2900 MHz
Nominal Output Power
IQ Modulator Voltage Gain
OP1dB
Carrier Feedthrough
Sideband Suppression
Quadrature Error
I/Q Amplitude Balance
Second Harmonic
Third Harmonic
Output IP2
Output IP3
Noise Floor
SYNTHESIZER SPECIFICATIONS
Internal LO Range
Figure of Merit (FOM)
1
Test Conditions/Comments
IQ modulator (±3 dB RF output range)
PLL LO range
RFOUT pin
Baseband VIQ = 1 V p-p differential
RF output divided by baseband input voltage
Min
2050
2500
6.2
2.2
12.9
−41.2
−42.4
±1
0.06
−67
−45.6
65.4
25.4
−157.8
5.5
1.5
12.1
−40.6
−37.7
0 to 2
0.06
−66
−47.1
63.8
27.2
−158.3
4.1
0.1
11.8
−41.5
−32.7
1 to 2.8
0.1
−67
−51.4
62.7
29.6
−157.5
2500
−221.4
2900
Typ
Max
3000
2900
Unit
MHz
MHz
dBm
dB
dBm
dBm
dBc
Degrees
dB
dBc
dBc
dBm
dBm
dBm/Hz
dBm
dB
dBm
dBm
dBc
Degrees
dB
dBc
dBc
dBm
dBm
dBm/Hz
dBm
dB
dBm
dBm
dBc
Degrees
dB
dBc
dBc
dBm
dBm
dBm/Hz
MHz
dBc/Hz/Hz
P
OUT
− P (f
LO
± (2 × f
BB
))
P
OUT
− P (f
LO
± (3 × f
BB
))
f1
BB
= 3.5 MHz, f2
BB
= 4.5 MHz, P
OUT
≈ −2 dBm per tone
f1
BB
= 3.5 MHz, f2
BB
= 4.5 MHz, P
OUT
≈ −2 dBm per tone
I/Q inputs = 0 V differential with 500 mV dc bias, 20 MHz carrier offset
RFOUT pin
Baseband VIQ = 1 V p-p differential
RF output divided by baseband input voltage
P
OUT
− P (f
LO
± (2 × f
BB
))
P
OUT
− P (f
LO
± (3 × f
BB
))
f1
BB
= 3.5 MHz, f2
BB
= 4.5 MHz, P
OUT
≈ −2 dBm per tone
f1
BB
= 3.5 MHz, f2
BB
= 4.5 MHz, P
OUT
≈ −2 dBm per tone
I/Q inputs = 0 V differential with 500 mV dc bias, 20 MHz carrier offset
RFOUT pin
Baseband VIQ = 1 V p-p differential
RF output divided by baseband input voltage
P
OUT
− P (f
LO
± (2 × f
BB
))
P
OUT
− P (f
LO
± (3 × f
BB
))
f1
BB
= 3.5 MHz, f2
BB
= 4.5 MHz, P
OUT
≈ −2 dBm per tone
f1
BB
= 3.5 MHz, f2
BB
= 4.5 MHz, P
OUT
≈ −2 dBm per tone)
I/Q inputs = 0 V differential with 500 mV dc bias, 20 MHz carrier offset
Synthesizer specifications referenced to the modulator output
Rev. 0 | Page 3 of 36
ADRF6704
Parameter
REFERENCE CHARACTERISTICS
REFIN Input Frequency
REFIN Input Capacitance
Phase Detector Frequency
MUXOUT Output Level
MUXOUT Duty Cycle
CHARGE PUMP
Charge Pump Current
Output Compliance Range
PHASE NOISE (FREQUENCY =
2500 MHz, f
PFD
= 38.4 MHz)
Programmable to 250 μA, 500 μA, 750 μA, 1000 μA
1
Closed loop operation (see
Figure 35
for loop filter design)
10 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
1 kHz to 10 MHz integration bandwidth
f
PFD
/2
f
PFD
f
PFD
× 2
f
PFD
× 3
f
PFD
× 4
Closed loop operation (see
Figure 35
for loop filter design)
10 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
1 kHz to 10 MHz integration bandwidth
f
PFD
/2
f
PFD
f
PFD
× 2
f
PFD
× 3
f
PFD
× 4
Closed loop operation (see
Figure 35
for loop filter design)
10 kHz offset
100 kHz offset
1 MHz offset
10 MHz offset
1 kHz to 10 MHz integration bandwidth
f
PFD
/2
f
PFD
f
PFD
× 2
f
PFD
× 3
f
PFD
× 4
Measured at RFOUT, frequency = 2700 MHz
Second harmonic
Third harmonic
LOP, LON
Divide by 2 circuit in LO path enabled
Divide by 2 circuit in LO path disabled
1× LO mode, into a 50 Ω load, LO buffer enabled
Externally applied 2× LO, PLL disabled
Externally applied 2× LO, PLL disabled
Rev. 0 | Page 4 of 36
Data Sheet
Test Conditions/Comments
REFIN, MUXOUT pins
11
4
22
Low (lock detect output selected)
High (lock detect output selected)
2.7
50
500
2.8
40
0.25
160
MHz
pF
MHz
V
V
%
μA
V
Min
Typ
Max
Unit
Integrated Phase Noise
Reference Spurs
−100.9
−100
−126
−148.3
0.37
−111
−87.3
−93.6
−92.8
−98.2
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
dBc
dBc
dBc
dBc
dBc
PHASE NOISE (
FREQUENCY =
2700 MHz, f
PFD
= 38.4 MHz)
Integrated Phase Noise
Reference Spurs
−97.7
−97.6
−126.1
−148.4
0.46
−110.4
−89.9
−92
−89.9
−94.5
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
dBc
dBc
dBc
dBc
dBc
PHASE NOISE (
FREQUENCY =
2900 MHz, f
PFD
= 38.4 MHz)
Integrated Phase Noise
Reference Spurs
−92.3
−96.4
−125.2
−148.5
0.62
−110.7
−90.9
−89.8
−92.1
−93.7
−44.4
−76.7
2500
5000
−2
0
50
2900
5800
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
°rms
dBc
dBc
dBc
dBc
dBc
dBc
dBc
MHz
MHz
dBm
dBm
Ω
RF OUTPUT HARMONICS
LO INPUT/OUTPUT
Output Frequency Range
LO Output Level at 2700 MHz
LO Input Level
LO Input Impedance
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