P4C1256
P4C1256
HIGH SPEED 32K x 8
STATIC CMOS RAM
FEATURES
High Speed (Equal Access and Cycle Times)
— 12/15/20/25/35 ns (Commercial)
— 15/20/25/35/45 ns (Industrial)
— 20/25/35/45/55/70 ns (Military)
Low Power
— 880 mW Active (Commercial)
Single 5V
±
10% Power Supply
Easy Memory Expansion Using
CE
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Fast t
OE
Automatic Power Down
Packages
—28-Pin 300 mil DIP and SOJ
—28-Pin 600 mil Ceramic DIP
—28-Pin LCC(350 mil x 550 mil)
—32-Pin LCC (450 mil x 550 mil)
DESCRIPTION
The P4C1256 is a 262,144-bit high-speed CMOS
static RAM organized as 32Kx8. The CMOS memory
requires no clocks or refreshing, and has equal access
and cycle times. Inputs are fully TTL-compatible. The
RAM operates from a single 5V±10% tolerance power
supply.
Access times as fast as 12 nanoseconds permit greatly
enhanced system operating speeds. CMOS is utilized
to reduce power consumption to a low level. The
P4C1256 is a member of a family of PACE RAM™ prod-
ucts offering fast access times.
The P4C1256 device provides asynchronous operation with
matching access and cycle times. Memory locations are
specified on address pins A
0
to A
14
. Reading is accom-
plished by device selection (CE and output enabling (OE)
while write enable (WE) remains HIGH. By presenting the
address under these conditions, the data in the addressed
memory location is presented on the data input/output pins.
The input/output pins stay in the HIGH Z state when either
CE
or
OE
is HIGH or
WE
is LOW.
Package options for the P4C1256 include 28-pin 300 mil
DIP and SOJ packages. For military temperature range,
Ceramic DIP and LCC packages are available.
FUNCTIONAL BLOCK DIAGRAM
ROW SELECT
A
•• •
PIN CONFIGURATIONS
VCC
A2
A1
A0
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
(8)
A
262,144-BIT
MEMORY
ARRAY
WE
A14
A13
A12
A2
A3
A4
A5
4
3
A0
2
1
NC
A3
A4
A5
A6
A7
A8
A9
NC
I/O1
5
6
7
8
9
10
11
12
32 31 30
29
28
27
26
25
24
23
22
WE
A14
A 13
A 12
A 11
NC
OE
A 10
CE
I/O8
I/O7
I/O
1
•••
••• •••
•••
A
11
OE
A
10
CE
I/0
8
I/0
7
I/0
6
I/0
5
I/0
4
A6
COLUMN I/O
INPUT
DATA
CONTROL
A7
A8
A9
• ••
•••
I/O
2
I/0
1
I/0
2
COLUMN
SELECT
13
21
14 15 16 17 18 19 20
I/O2
I/O3
GND
I/O4
I/O5
I/O6
NC
I/0
3
GND
WE
•••
•••
CE
OE
A
(7)
A
DIP (P5, C5, D5-1), SOJ (J5)
TOP VIEW
1519B
32 LCC (L6)
TOP VIEW
See Selection Guide page for 28-pin LCC
Means Quality, Service and Speed
1Q97
117
P4C1256
MAXIMUM RATINGS
(1)
Symbol
V
CC
Parameter
Power Supply Pin with
Respect to GND
Terminal Voltage with
Respect to GND
(up to 7.0V)
Operating Temperature
Value
–0.5 to +7
–0.5 to
V
CC
+0.5
–55 to +125
Unit
V
Symbol
T
BIAS
T
STG
P
T
I
OUT
Parameter
Temperature Under
Bias
Storage Temperature
Power Dissipation
DC Output Current
Value
–55 to +125
–65 to +150
1.0
50
Unit
°C
°C
W
mA
V
TERM
T
A
V
°C
RECOMMENDED OPERATING
TEMPERATURE AND SUPPLY VOLTAGE
Grade(2)
Military
Industrial
Commercial
Ambient
Temperature
–55°C to +125°C
–40°C to +85°C
0°C to +70°C
GND
0V
0V
0V
V
CC
5.0V
±
10%
5.0V
±
10%
5.0V
±
10%
CAPACITANCES
(4)
V
CC
= 5.0V, T
A
= 25°C, f = 1.0MHz
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Conditions Typ. Unit
V
IN
= 0V
8
10
pF
pF
Output Capacitance V
OUT
= 0V
DC ELECTRICAL CHARACTERISTICS
Over recommended operating temperature and supply voltage
(2)
Symbol
V
IH
V
IL
V
HC
V
LC
V
OL
V
OH
I
LI
I
LO
I
SB
Parameter
Input High Voltage
Input Low Voltage
CMOS Input High Voltage
CMOS Input Low Voltage
Output Low Voltage
(TTL Load)
Output High Voltage
(TTL Load)
Input Leakage Current
I
OL
= +8 mA, V
CC
= Min.
I
OH
= –4 mA, V
CC
= Min.
V
CC
= Max.
V
IN
= GND to V
CC
Mil.
Ind./Com’l.
2.4
–10
–5
–10
–5
___
___
___
___
+10
+5
+10
+5
45
30
20
10
Test Conditions
P4C1256
Unit
Min
Max
V
CC
+0.5 V
2.2
0.8
–0.5
(3)
V
CC
–0.2 V
CC
+0.5
–0.5
(3)
0.2
0.4
V
V
V
V
V
µA
µA
Output Leakage Current
V
CC
= Max.,
CE
= V
IH
,
Mil.
V
OUT
= GND to V
CC
Ind./Com’l.
CE
≥
V
IH
or
Mil.
Standby Power Supply
Current (TTL Input Levels) CE
2
≤V
IL
, V
CC
= Max Ind./Com’l.
f = Max., Outputs Open
Standby Power Supply
Current
(CMOS Input Levels)
CE
≥
V
HC
or
Mil.
CE
2
≤V
LC
, V
CC
= Max Ind./Com’l.
f = 0, Outputs Open
V
IN
≤
V
LC
or V
IN
≥
V
HC
mA
I
SB1
mA
n/a = Not Applicable
Notes:
1. Stresses greater than those listed under MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAXIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
118
P4C1256
POWER DISSIPATION CHARACTERISTICS VS. SPEED
Symbol
Parameter
Temperature
Range
Commercial
Military
–12
170
N/A
N/A
–15
160
170
N/A
–20
155
165
170
–25
150
160
165
–35
145
155
160
–45
N/A
150
155
–55
N/A
N/A
150
–70
N/A
N/A
150
Unit
mA
mA
mA
I
CC
Dynamic Operating Current* Industrial
*V
CC
= 5.5V. Tested with outputs open. f = Max. Switching inputs are 0V and 3V.
CE
= V
IL
,
OE
= V
IH
.
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(V
CC
= 5V
±
10%, All Temperature Ranges)
(2)
Sym.
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
Parameter
-12
-15
15
-20
20
-25
25
-35
35
-45
45
-55
55
-70
70
Unit
ns
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Read Cycle Time 12
Address Access
Time
Chip Enable
Access Time
Output Hold from
Address Change
Chip Enable to
Output in Low Z
Chip Disable to
Output in High Z
Output Enable
Low to Data
Valid
Output Enable
Low to Low Z
Output Enable
High to High Z
Chip Enable to
Power Up Time
Chip Disable to
Power Down
Time
0
12
0
5
0
15
2
2
5
5
12
12
2
2
8
7
15
15
2
2
20
20
3
3
9
9
25
25
3
3
11
10
35
35
3
3
15
15
45
45
3
3
20
20
55
55
3
3
25
25
70
70
ns
ns
ns
ns
30
30
ns
ns
t
OLZ
t
OHZ
t
PU
t
PD
0
7
0
9
0
20
0
11
0
20
0
15
0
20
0
20
0
25
0
25
0
30
0
30
0
35
ns
ns
ns
ns
119
P4C1256
OE
READ CYCLE NO. 1 (OE CONTROLLED)
(1)
tRC
(5)
ADDRESS
tAA
OE
tOE
t
OLZ
CE
(4)
tOH
tAC
tAC
DATA OUT
(4)
tHZ
(4)
tOHZ
(4)
READ CYCLE NO. 2 (ADDRESS CONTROLLED)
t
RC (5)
ADDRESS
t
AA
t
OH
DATA OUT
PREVIOUS DATA VALID
DATA VALID
READ CYCLE NO. 3 (CE CONTROLLED)
CE
tRC
CE
tLZ(8)
DATA OUT
ICC
VCC SUPPLY
CURRENT
tAC
DATA VALID
tHZ
HIGH IMPEDANCE
tPU
tPD
ISB
Notes:
1.
WE
is HIGH for READ cycle.
2.
CE
1
is LOW, CE
2
is HIGH and
OE
is LOW for READ cycle.
3. ADDRESS must be valid prior to, or coincident with
CE
1
transition
LOW .
4. Transition is measured
±
200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is
sampled and not 100% tested.
5. READ Cycle Time is measured from the last valid address to the first
transitioning address.
120
P4C1256
AC CHARACTERISTICS—WRITE CYCLE
(V
CC
= 5V
±
10%, All Temperature Ranges)
(2)
Sym.
t
WC
t
CW
Parameter
-12
-15
15
10
-20
20
15
-25
25
18
-35
35
22
-45
45
30
-55
55
35
-70
70
40
Min Max Min Max Min Max Min Max Min Max Min Max Min Max Min Max
Unit
ns
ns
Write Cycle Time 12
Chip Enable
Time to End of
Write
Address Valid to
End of Write
Address Set-up
Time
Write Pulse
Width
Address Hold
Time
Data Valid to
End of Write
Date Hold Time
Write Enable to
Output in High Z
Output Active
3
from End of Write
9
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
9
0
9
0
8
0
7
10
0
11
0
9
0
8
3
15
0
15
0
11
0
10
3
20
0
18
0
13
0
11
3
25
0
22
0
15
0
15
5
35
0
25
0
20
0
18
5
40
0
30
0
25
0
25
0
45
0
35
0
30
0
30
0
ns
ns
ns
ns
ns
ns
ns
ns
WRITE CYCLE NO. 1 (WE CONTROLLED)
(6)
WE
tWC
ADDRESS
tCW
CE
(9)
tAW
tWP
WE
tAS
DATA IN
tWZ
(7)
(4)
tAH
tDW
DATA VALID
tDH
tOW
(4,7)
DATA OUT
DATA UNDEFINED
HIGH IMPEDANCE
Notes:
6.
CE
1
and
WE
must be LOW for WRITE cycle.
7.
OE
is LOW for this WRITE cycle to show t
WZ
and t
OW
.
8. If
CE
1
goes HIGH simultaneously with
WE
HIGH, the output remains
in a high impedance state.
9. Write Cycle Time is measured from the last valid address to the first
transitioning address.
121
京公网安备 11010802033920号
EEWORLD
