PCX8548EMGHYUANGA datasheet, PDF

Datasheet> All Categories > The embedded processor and controller> Microcontrollers and processors> PCX8548EMGHYUANGA

PCX8548EMGHYUANGA: DescriptionMicroprocessor, 32-Bit, 800MHz, CMOS, PBGA783, 29 X 29 MM, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FLIP CHIP, BGA-783; CategoryThe embedded processor and controller Microcontrollers and processors; File Size2MB，103 Pages; Manufacturere2v technologies

Download Datasheet Parametric View All

PCX8548EMGHYUANGA Overview

Microprocessor, 32-Bit, 800MHz, CMOS, PBGA783, 29 X 29 MM, 1 MM PITCH, ROHS COMPLIANT, CERAMIC, FLIP CHIP, BGA-783

PCX8548EMGHYUANGA Parametric

Parameter Name	Attribute value
Maker	e2v technologies
Parts packaging code	BGA
package instruction	BGA,
Contacts	783
Reach Compliance Code	compliant
ECCN code	3A001.A.3
Address bus width	64
bit size	32
boundary scan	YES
maximum clock frequency	133 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-PBGA-B783
JESD-609 code	e1
length	29 mm
low power mode	YES
Number of terminals	783
Package body material	PLASTIC/EPOXY
encapsulated code	BGA
Package shape	SQUARE
Package form	GRID ARRAY
Certification status	Not Qualified
Maximum seat height	3.38 mm
speed	800 MHz
Maximum supply voltage	1.155 V
Minimum supply voltage	1.045 V
Nominal supply voltage	1.1 V
surface mount	YES
technology	CMOS
Terminal surface	TIN SILVER COPPER
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
width	29 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

Preview

Download Datasheet

View All

PC8548E

PowerQUICC III Integrated Processor

Datasheet -

Preliminary Specification

Features

•

Embedded e500 Core, Initial Offerings up to 1.2 GHz

– Dual Dispatch Superscalar, 7-stage Pipeline Design with out-of-order Issue and

Execution

– 3065 MIPS at 1333 MHz (Estimated Dhrystone 2.1)

36-bit Physical Addressing

Enhanced Hardware and Software Debug Support

Double-precision Embedded Scalar and Vector Floating-point APUs

Memory Management Unit (MMU)

Integrated L1/L2 Cache

– L1 Cache-32 KB Data and 32 KB Instruction Cache with Line-locking Support

– L2 Cache-512 KB (8-Way Set Associative); 512 KB/256 KB/128 KB/64 KB Can Be Used As SRAM

– L1 and L2 Hardware Coherency

– L2 Configurable As SRAM, Cache and I/O Transactions Can Be Stashed Into L2 Cache Regions

Integrated DDR Memory Controller With Full ECC Support, Supporting:

– 200 MHz Clock Rate (400 MHz Data Rate), 64-bit, 2.5V/2.6V I/O, DDR SDRAM

Integrated Security Engine Supporting DES, 3DES, MD-5, SHA-1/2, AES, RSA, RNG, Kasumi F8/F9 and ARC-4 Encryption

Algorithms

Four On-chip Triple-speed Ethernet Controllers (GMACs) Supporting 10- and 100-Mbps, and 1-Gbps Ethernet/IEEE*802.3

Networks with MII, RMII, GMII, RGMII, RTBI and TBI Physical Interfaces

– TCP/IP Checksum Acceleration

– Advanced QoS Features

General-purpose I/O (GPIO)

Serial RapidIO and PCI Express High-speed Interconnect Interfaces, Supporting

– Single x8 PCI Express, or Single x4 PCI Express and Single 4x Serial RapidIO

On-chip Network (OCeaN) Switch Fabric

Multiple PCI Interface Support

– 64-bit PCI 2.2 Bus Controller (Up to 66 MHz, 3.3V I/O)

– 64-bit PCI-X Bus Controller (Up to 133 MHz, 3.3V I/O), or Flexibility to Configure Two 32-bit PCI Controllers

166 MHz, 32-bit, 3.3V I/O, Local Bus with Memory Controller

Integrated Four-channel DMA Controller

Dual I2C and Dual Universal Asynchronous Receiver/Transmitter (DUAR) Support

Programmable Interrupt Controller (PIC), IEEE 1149.1 JTAG Test Access Port

1.1V Core Voltage with 3.3V and 2.5V I/O, 783-pin HITCE Package

•

Visit our website: www.e2v.com

for the latest version of the datasheet

e2v semiconductors SAS 2008

0831C–HIREL–04/08

PC8548E [Preliminary]

2. Features Overview

The following list provides an overview of the PC8548E feature set:

• High-performance 32-bit Book E–enhanced core that implements the PowerPC

architecture

– 32-Kbyte L1 instruction cache and 32-Kbyte L1 data cache with parity protection. Caches

can be locked entirely or on a per-line basis, with separate locking for instructions and data.

– Signal-processing engine (SPE) APU (auxiliary processing unit). Provides an extensive

instruction set for vector (64-bit) integer and fractional operations. These instructions use

both the upper and lower words of the 64-bit GPRs as they are defined by the SPE APU.

– Double-precision floating-point APU. Provides an instruction set for double-precision (64-bit)

floating-point instructions that use the 64-bit GPRs.

– 36-bit real addressing

– Embedded vector and scalar single-precision floating-point APUs. Provide an instruction set

for single-precision (32-bit) floating-point instructions.

– Memory management unit (MMU). Especially designed for embedded applications. Supports

4-Kbyte–4-Gbyte page sizes.

– Enhanced hardware and software debug support

– Performance monitor facility that is similar to, but separate from, the PC8548E performance

monitor

The e500 defines features that are not implemented on this device. It also generally defines some

features that this device implements more specifically. An understanding of these differences can be

critical to ensure proper operations.

• 512-Kbyte L2 cache/SRAM

– Flexible configuration.

– Full ECC support on 64-bit boundary in both cache and SRAM modes

– Cache mode supports instruction caching, data caching, or both.

– External masters can force data to be allocated into the cache through programmed memory

ranges or special transaction types (stashing).

– 1, 2, or 4 ways can be configured for stashing only.

– Eight-way set-associative cache organization (32-byte cache lines)

– Supports locking entire cache or selected lines. Individual line locks are set and cleared

through Book E instructions or by externally mastered transactions.

– Global locking and flash clearing done through writes to L2 configuration registers

– Instruction and data locks can be flash cleared separately.

– SRAM features include the following:

– I/O devices access SRAM regions by marking transactions as snoopable (global).

– Regions can reside at any aligned location in the memory map.

– Byte-accessible ECC is protected using read-modify-write transaction accesses for smaller-

than-cache-line accesses.

• Address translation and mapping unit (ATMU)

– Eight local access windows define mapping within local 36-bit address space.

– Inbound and outbound ATMUs map to larger external address spaces.

– Three inbound windows plus a configuration window on PCI/PCI-X and PCI Express

0831C–HIREL–04/08

e2v semiconductors SAS 2008

Recommended Resources

Rectifier circuit a for bipolar voltage output from a double-winding transformer

TLG-1-, 2, 3 type thyristor automatic excitation device circuit

Sound and light sounder and its application circuit

Photovoltaic cell-silicon transistor control circuit

Application circuit example circuit diagram

What is the minimum capacitance that AD7746 can measure?: Dear experts, I need help: Looking at the AD7746 data sheet, the input range is plus or minus 4pF, but my capacitive sensor output is a few tenths of a pF. Can the AD7746 measure this?...; zhangyao7751 ADI Reference Circuit

Read the good book "Operational Amplifier Parameter Analysis and LTspice Application Simulation" 01 LTspice Installation and Example Run: Thanks to the forum for providing me with this opportunity to learn LTspice in depth. I also use LTspice in my daily work, but I haven't studied it seriously yet.Installing LTspice LTspice can be down...; nemo1991 Analog electronics

Bus reset, turn off external clock!: Hardware: s3c2410 Many buses use the divided clock of 2410. After I set the relevant registers of the bus, will the register settings be lost if I turn off the clock? How do I reset the bus? Thank you...; jiashengit Embedded System

Regarding the hard drive problem!: Could any expert help me explain the principle of hard disk drive? I need to write a detailed design document of hard disk drive recently, but I am not very clear about the hard disk. Thanks!...; wangjun01 Embedded System

Hello world FPGA (cyclone4) development board experience post 03: The schematic diagram of kdy is in place~ I tried the demo written in verilog and it went smoothly~. The cyan LED color is very good~Then I wanted to try hellow world. I used NIOS and basically used t...; astwyg FPGA/CPLD

The LaunchPad Boosterpack I made: Seeing that launchpad has various boosterpacks, I also drew a general purpose boosterpackDirectly on the pictureThere are GND connection test points at the three corners for testing.A 5mm spacing powe...; wstt Microcontroller MCU

Development of automotive CAN bus data recorder

1. Introduction Since the 1980s, with the continuous development of automotive electronic technology, there are more and more electronic control units in automobiles, such as electronic fuel i...[Details]
How to enable analog engineers to achieve digital power conversion

Analog engineers have traditionally struggled with complexity when designing power supplies that required multiple outputs, dynamic load sharing, hot-swap, or extensive fault-handling capabilities....[Details]
The reason for the light decay of white LEDs: the decline of phosphor performance

The reason for the light decay of white LEDs: the decline of phosphor performance So far, the rapid decline of the luminous performance of white light LEDs, especially low-power white light LE...[Details]
Improving the efficiency of gear motors

With concerns about the growing energy crisis, motor efficiency has become an important and timely topic. This is because motors use 63% to 70% of the electricity produced in the United States and ...[Details]
Design of sensor experimental platform based on wireless sensor network technology

0 Introduction There are many types of sensors, and the working principles, measurement targets and measurement environments of different types of sensors vary greatly. The corresponding detection s...[Details]
Introduction to Clock Distribution System Design in Medical Imaging

The demand for improved healthcare environments is endless, so medical imaging equipment with higher resolution is needed to better observe the human body. High resolution brings problems with sign...[Details]
Is LED lighting a "lamp" or a "lamp fixture"?

1 Overview In the field of traditional lighting, the concepts and definitions of lamps and lamps are clear. Lamps and lamps have their own applicable product standards, supporting technical st...[Details]
Battery clamp quick release method

Battery clamps, commonly known as battery connectors, come in two sizes depending on the thickness of the battery terminals. One is the battery clamp used on thick terminals, with a positive termin...[Details]
How to reduce electrostatic interference? Electrostatic shielding can help

Electrostatic coupling and interference occur when a charged object is close to the input of the circuit being measured. At low impedance, the effects of interference are not noticeable because th...[Details]
In-depth analysis of Ethernet power supply

Features POE technology can ensure the safety of existing structured cabling while ensuring the normal operation of the existing network and minimizing costs. The IEEE 802.3af standard is ...[Details]
Application of ASI fieldbus in spent anode washing and stacking unit

1. Introduction AS-Interface bus technology is an intelligent network that uses a single cable to connect sensors and actuators to controllers, transmit data, and provide power. It can be used...[Details]
Principle and application of stepper motor control chip UDN2916LB

UDN2916LB is a two-phase stepper motor bipolar driver integrated circuit launched by SANKEN. It can drive dual-winding bipolar stepper motors and is particularly suitable for controlling dual-step ...[Details]
SL11R MCU External Memory Expansion

SL11R is a 16-bit RISC microcontroller with a USB interface produced by Scanlogic. Its core processing speed reaches 48MIPS. It has rich hardware resources and 32-bit programmable I/O ports, and ca...[Details]
Realizing fixed-ratio image zooming based on FPGA

Abstract: Based on FPGA hardware, the image scaling with fixed magnification is realized. The 2D convolution operation is decomposed into 2 1D convolution operations. The input original image pixel...[Details]
Design of motion estimation based on FPGA

Abstract: A motion estimation design for video images is implemented using a powerful FPGA. The search method used is a three-step search method. When designing the scheme, this paper uses the rela...[Details]

Shortcut: E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF EG EH EI EJ EK EL EM EN EO EP EQ ER ES ET EU EV EW EX EY EZ F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF FG FH FI FJ FK FL FM FN FO FP FQ FR FS FT FU FV FW FX FY FZ G0 G1 G2 G3 G4 G5 G6 G7 G8 G9 GA GB GC GD GE GF GG GH GI GJ GK GL GM GN GO GP GQ GR GS GT GU GV GW GX GZ H0 H1 H2 H3 H4 H5 H6 H7 H8 HA HB HC HD HE HF HG HH HI HJ HK HL HM HN HO HP HQ HR HS HT HU HV HW HX HY HZ I1 I2 I3 I4 I5 I6 I7 IA IB IC ID IE IF IG IH II IK IL IM IN IO IP IQ IR IS IT IU IV IW IX J0 J1 J2 J6 J7 JA JB JC JD JE JF JG JH JJ JK JL JM JN JP JQ JR JS JT JV JW JX JZ K0 K1 K2 K3 K4 K5 K6 K7 K8 K9 KA KB KC KD KE KF KG KH KI KJ KK KL KM KN KO KP KQ KR KS KT KU KV KW KX KY KZ

Popular Components