P4C164LL
VERY LOW POWER 8Kx8
STATIC CMOS RAM
FEATURES
V
CC
Current (Commercial/Industrial)
— Operating: 55 mA
— CMOS Standby: 3 µA
Access Times
—80/100 (Commercial or Industrial)
—90/120 (Military)
Single 5 Volts ±10% Power Supply
Easy Memory Expansion Using
CE
1
,
CE
2
and
OE
Inputs
Common Data I/O
Three-State Outputs
Fully TTL Compatible Inputs and Outputs
Advanced CMOS Technology
Automatic Power Down
Packages
—28-Pin 300 and 600 mil DIP
—28-Pin 330 mil SOP
DESCRIPTIOn
The P4C164LL is a 64K density low power CMOS static
RAM organized as 8Kx8. The CMOS memory requires
no clocks or refreshing, and has equal access and cycle
times. Inputs are fully TTL-compatible. The RAM operates
from a single 5V±10% tolerance power supply.
Access times of 80 and 100 ns are available for commercial
and industrial temperatures; access times of 90 and 100
ns are available for military temperature. CMOS is utilized
to reduce power consumption to a low level.
The P4C164LL device provides asynchronous operation
with matching access and cycle times.
Memory locations are specified on address pins A
0
to A
12
.
Reading is accomplished by device selection (CE
1
LOW,
CE
2
HIGH ) and output enabling (OE) while write enable
(WE) remains HIGH. By presenting the address under
these conditions, the data in the addressed memory loca-
tion is presented on the data input/output pins. The input/
output pins stay in the HIGH Z state when either
CE
1
or
OE
is HIGH or
WE
or CE
2
is LOW.
Package options for the P4C164LL include 28-pin 300 and
600 mil DIP and 28-pin 330 mil SOP packages.
FUnCTIOnAL BLOCk DIAgRAM
PIn COnFIgURATIOnS
DIP (P5, P6, C5-1), SOP (S5)
TOP VIEW
Document #
SRAM116
REV C
Revised March 2010
P4C164LL - VERY LOW POWER 8K x 8 STATIC CMOS RAM
RECOMMEnDED OPERATIng TEMPERATURE & SUPPLY VOLTAgE
grade
Commercial
Industrial
Military
Ambient Temp
0°C to 70°C
-40°C to +85°C
-55°C to +125°C
Supply Voltage
4.5V ≤ V
CC
≤ 5.5V
4.5V ≤ V
CC
≤ 5.5V
4.5V ≤ V
CC
≤ 5.5V
MAxIMUM RATIngS
(1)
Symbol
V
CC
V
TERM
T
A
S
TG
I
OUT
I
LAT
Parameter
Supply Voltage with Respect to GND
Terminal Voltage with Respect to GND (up to 7.0V)
Operating Ambient Temperature
Storage Temperature
Output Current into Low Outputs
Latch-up Current
> 200
Min
-0.5
-0.5
-55
-65
Max
7.0
VCC + 0.5
125
150
25
Unit
V
V
°C
°C
mA
mA
DC ELECTRICAL CHARACTERISTICS
Sym Parameter
V
OH
V
OL
V
IH
V
IL
Output High Voltage
(I/O
0
- I/O
7
)
Output Low Voltage
(I/O
0
- I/O
7
)
Input High Voltage
Input Low Voltage
(Over Recommended Operating Temperature & Supply Voltage)
(2)
Test Conditions
I
OH
= -1mA, V
CC
= 4.5V
I
OL
= 2.1mA
2.2
-0.5
(3)
Com / Ind
Min
2.4
Max
Unit
V
0.4
V
CC
+ 0.3
0.8
+2
V
V
V
-2
-5
-2
-10
I
LI
Input Leakage Current
GND ≤ V
IN
≤ V
CC
µA
Military
Com / Ind
Military
Com / Ind
Military
Com / Ind
Military
+5
+2
µA
+10
100
µA
400
3
µA
25
I
LO
Output Leakage Current
GND ≤ V
OUT
≤ V
CC
CE
1
≥ V
IH
I
SB
V
CC
Current
TTL Standby Current
(TTL Input Levels)
V
CC
Current
CMOS Standby Current
(CMOS Input Levels)
V
CC
= 5.5V, I
OUT
= 0 mA
CE
1
= V
IH
or CE
2
= V
IL
I
SB1
V
CC
= 5.5V, I
OUT
= 0 mA
CE
1
≥ V
CC
- 0.2V or CE
2
≤ 0.2V
notes:
1. Stresses greater than those listed under MAxIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of this specification
is not implied. Exposure to MAxIMUM rating conditions for extended
periods may affect reliability.
2. Extended temperature operation guaranteed with 400 linear feet per
minute of air flow.
3. Transient inputs with V
IL
and I
IL
not more negative than –3.0V and
–100mA, respectively, are permissible for pulse widths up to 20 ns.
4. This parameter is sampled and not 100% tested.
Document #
SRAM116
REV C
Page 2
P4C164LL - VERY LOW POWER 8K x 8 STATIC CMOS RAM
CAPACITAnCES
(4)
Symbol
C
IN
C
OUT
Parameter
Input Capacitance
Output Capacitance
Test Conditions
V
IN
= 0V
V
OUT
= 0V
Max
7
9
Unit
pF
pF
POWER DISSIPATIOn CHARACTERISTICS VS. SPEED
Symbol
I
CC
Parameter
Dynamic Operating Current
Temperature Range
Com / Ind / Military
*
-80
55
-90
55
-100
55
-120
55
Unit
mA
* Tested with outputs open and all address and data inputs changing at the maximum write-cycle rate. The device is continuously
enabled for writing, i.e.
CE
1
and
WE
≤ V
IL
(max),
OE
is high. Switching inputs are 0V and 3V.
AC ELECTRICAL CHARACTERISTICS—READ CYCLE
(Over Recommended Operating Temperature & Supply Voltage)
Sym
t
RC
t
AA
t
AC
t
OH
t
LZ
t
HZ
t
OE
t
OLZ
t
OHZ
t
PU
t
PD
Parameter
Read Cycle Time
Address Access Time
Chip Enable Access Time
Output Hold from Address Change
Chip Enable to Output in Low Z
Chip Disable to Output in High Z
Output Enable Low to Data Valid
Output Enable Low to Low Z
Output Enable High to High Z
Chip Enable to Power Up Time
Chip Disable to Power Down Time
0
80
5
20
0
90
10
10
30
40
5
20
0
100
-80
Min
80
80
80
10
10
30
40
5
20
0
120
Max
Min
90
90
90
10
10
30
40
5
20
-90
Max
Min
100
100
100
10
10
30
40
-100
Max
Min
120
120
120
-120
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Document #
SRAM116
REV C
Page 3
P4C164LL - VERY LOW POWER 8K x 8 STATIC CMOS RAM
TIMIng WAVEFORM OF READ CYCLE nO. 1 (OE COnTROLLED)
(1)
TIMIng WAVEFORM OF READ CYCLE nO. 2 (ADDRESS COnTROLLED)
TIMIng WAVEFORM OF READ CYCLE nO. 3 (CE
1
,
CE
2
COnTROLLED)
notes:
5.
WE
is HIGH for READ cycle.
6.
CE
1
is LOW, CE
2
is HIGH and
OE
is LOW for READ cycle.
7. ADDRESS must be valid prior to, or coincident with
CE
1
transition LOW
and CE
2
transition HIGH.
8. Transition is measured ± 200 mV from steady state voltage prior to
change, with loading as specified in Figure 1. This parameter is sampled
and not 100% tested.
9. Read Cycle Time is measured from the last valid address to the first
transitioning address.
10. Transitions caused by a chip enable control have similar delays ir-
respective of whether
CE
1
or CE
2
causes them.
Document #
SRAM116
REV C
Page 4
P4C164LL - VERY LOW POWER 8K x 8 STATIC CMOS RAM
AC CHARACTERISTICS—WRITE CYCLE
Symbol
t
WC
t
CW
t
AW
t
AS
t
WP
t
AH
t
DW
t
DH
t
WZ
t
OW
Parameter
Write Cycle Time
Chip Enable Time to End of Write
Address Valid to End of Write
Address Setup Time
Write Pulse Width
Address Hold Time
Data Valid to End of Write
Data Hold Time
Write Enable to Output in High Z
Output Active from End of Write
(Over Recommended Operating Temperature & Supply Voltage)
-80
Min
80
70
70
0
60
0
40
0
30
10
10
Max
Min
90
80
80
0
60
0
40
0
30
10
-90
Max
Min
100
80
80
0
60
0
40
0
30
10
-100
Max
Min
120
100
100
0
60
0
40
0
30
-120
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
TIMIng WAVEFORM OF WRITE CYCLE nO. 1 (WE COnTROLLED)
(6)
Notes:
11.
CE
1
and
WE
must be LOW, and CE
2
HIGH for WRITE cycle.
12.
OE
is LOW for this WRITE cycle to show t
WZ
and t
OW
.
13. If
CE
1
goes HIGH, or CE
2
goes LOW, simultaneously with
WE
HIGH,
the output remains in a high impedance state
14. Write Cycle Time is measured from the last valid address to the first
transitioning address.
Document #
SRAM116
REV C
Page 5
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