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23S08E-1HDC8

Description
PLL Based Clock Driver, 23S Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, SOIC-16
Categorylogic    logic   
File Size76KB,11 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

23S08E-1HDC8 Overview

PLL Based Clock Driver, 23S Series, 8 True Output(s), 0 Inverted Output(s), PDSO16, SOIC-16

23S08E-1HDC8 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
Parts packaging codeSOIC
package instructionSOP, SOP16,.25
Contacts16
Reach Compliance Code_compli
series23S
Input adjustmentSTANDARD
JESD-30 codeR-PDSO-G16
JESD-609 codee0
Logic integrated circuit typePLL BASED CLOCK DRIVER
MaximumI(ol)0.012 A
Humidity sensitivity level1
Number of functions1
Number of inverted outputs
Number of terminals16
Actual output times8
Maximum operating temperature70 °C
Minimum operating temperature
Output characteristics3-STATE
Package body materialPLASTIC/EPOXY
encapsulated codeSOP
Encapsulate equivalent codeSOP16,.25
Package shapeRECTANGULAR
Package formSMALL OUTLINE
Peak Reflow Temperature (Celsius)240
power supply3.3 V
Certification statusNot Qualified
Same Edge Skew-Max(tskwd)0.2 ns
Maximum supply voltage (Vsup)3.6 V
Minimum supply voltage (Vsup)3 V
Nominal supply voltage (Vsup)3.3 V
surface mountYES
Temperature levelCOMMERCIAL
Terminal surfaceTin/Lead (Sn85Pb15)
Terminal formGULL WING
Terminal pitch1.27 mm
Terminal locationDUAL
Maximum time at peak reflow temperature20
minfmax200 MHz
Base Number Matches1
IDT23S08E
3.3V ZERO DELAY CLOCK MULTIPLIER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
3.3V ZERO DELAY CLOCK
MULTIPLIER, SPREAD
SPECTRUM COMPATIBLE
FEATURES:
DESCRIPTION:
IDT23S08E
• Phase-Lock Loop Clock Distribution for Applications ranging
from 10MHz to 200MHz operating frequency
• Distributes one clock input to two banks of four outputs
• Separate output enable for each output bank
• External feedback (FBK) pin is used to synchronize the outputs
to the clock input
• Output Skew <200 ps
• Low jitter <200 ps cycle-to-cycle
• 1x, 2x, 4x output options (see table):
– IDT23S08E-1 1x
– IDT23S08E-2 1x, 2x
– IDT23S08E-3 2x, 4x
– IDT23S08E-4 2x
– IDT23S08E-1H, -2H, and -5H for High Drive
• No external RC network required
• Operates at 3.3V V
DD
• Spread spectrum compatible
• Available in SOIC and TSSOP packages
The IDT23S08E is a high-speed phase-lock loop (PLL) clock multiplier. It
is designed to address high-speed clock distribution and multiplication applica-
tions. The zero delay is achieved by aligning the phase between the incoming
clock and the output clock, operable within the range of 10 to 200MHz.
The IDT23S08E has two banks of four outputs each that are controlled via
two select addresses. By proper selection of input addresses, both banks can
be put in tri-state mode. In test mode, the PLL is turned off, and the input clock
directly drives the outputs for system testing purposes. In the absence of an
input clock, the IDT23S08E enters power down. In this mode, the device will
draw less than 12µA for Commercial Temperature range and less than 25µA
for Industrial temperature range, and the outputs are tri-stated.
The IDT23S08E is available in six unique configurations for both pre-
scaling and multiplication of the Input REF Clock. (See available options
table.)
The PLL is closed externally to provide more flexibility by allowing the user
to control the delay between the input clock and the outputs.
The IDT23S08E is characterized for both Industrial and Commercial
operation.
NOTE: EOL for non-green parts to occur on 5/13/10 per
PDN U-09-01
FUNCTIONAL BLOCK DIAGRAM
(-3, -4)
FBK
REF
16
1
2
(-5)
2
PLL
3
2
CLKA1
CLKA2
14
CLKA3
15
CLKA4
S2
S1
8
9
Control
Logic
(-2, -3)
2
6
CLKB1
7
CLKB2
10
CLKB3
11
CLKB4
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c
2006
Integrated Device Technology, Inc.
AUGUST 2009
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