IRUH330118AKC datasheet, PDF - EEWORLD Datasheet

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IRUH330118AKC: Description3.3 V FIXED POSITIVE LDO REGULATOR, 0.4 V DROPOUT, DFP8; CategoryPower/power management The power supply circuit; File Size160KB，9 Pages; ManufacturerInternational Rectifier （ Infineon ）; Websitehttp://www.irf.com/

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IRUH330118AKC Overview

3.3 V FIXED POSITIVE LDO REGULATOR, 0.4 V DROPOUT, DFP8

IRUH330118AKC Parametric

Parameter Name	Attribute value
Maker	International Rectifier （ Infineon ）
Parts packaging code	DFP
package instruction	,
Contacts	8
Reach Compliance Code	unknown
ECCN code	EAR99
JESD-30 code	S-XDFP-F8
Number of terminals	8
Package body material	UNSPECIFIED
Package shape	SQUARE
Package form	FLATPACK
Certification status	Not Qualified
Regulator type	FIXED POSITIVE SINGLE OUTPUT LDO REGULATOR
surface mount	YES
Terminal form	FLAT
Terminal location	DUAL
Base Number Matches	1

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PD-97530C

(5962F1023503K)

IRUH330118AK

Radiation Hardended Ultra Low Dropout

IRUH330118AP

Fixed Positive Linear Regulator

+3.3V

to +1.8V

OUT

@3.0A

Product Summary

Part Number

IRUH330118AK

IRUH330118AP

3.0A

3.3V

OUT

1.8V

8-LEAD FLAT PACK

Description

The IRUH330118 is a space qualified, ultra low dropout

linear regulator designed specifically for applications

requiring high reliability, low noise and radiation hardness.

Features

Silicon On Insulator (SOI) CMOS Regulator

Absolute Maximum Ratings

Parameter

Power Dissipation @ T

= 125°C

Maximum Output Current @ Maximum

Power Dissipation with no Derating

Non-Operating Input Voltage

Operating Input Voltage

Ground

Shutdown Pin Voltage

Output Pin Voltage

Operating Case Temperature Range

Storage Temperature Range

Maximmum Junction Temperature

Lead Temperature (Soldering 10sec)

Pass Transistor Thermal Resistance, Junction to Case

GND

SHDN

OUT

THJC

IC, CMOS Latch-Up Immune,

Inherently Rad Hard

Total Dose Capability up to 300Krads(Si)

(Condition A); Tested to 500Krad (Si)

ELDRS up to 100Krad(Si) (Condition D)

SEU Immune up to LET = 80 MeV*cm

/mg

Space Level Screened

Fast Transient Response

Timed Latch-Off Over-Current Protection

Internal Thermal Protection

On/Off Control via Shutdown Pin, Power

Sequencing Easily Implemented

Isolated Hermetic 8-Lead Flat Pack

Ensures Higher Reliability

This part is also available in MO-078 Package

as IRUH330118BK / IRUH330118BP

Min.

-0.3

2.9

-0.3

-55

-65

Symbol

Max.

See Fig 4

+8.0

6.4

0.3

+ 0.3

+140

+150

+300

1.0

Units

°C

°C/W

www.irf.com

05/18/12

IRUH330118AK

IRUH330118AP

Input Capacitance

Input bypass capacitors: Two (0.1µF and 1µF) ceramics and two 100µF low ESR tantalums (AVX

TPS or equivalent), placed very close to the V

Pin are required for proper operation. When the

input voltage supply capacitance is more than 4 inches from the device, additional input

capacitance is recommended. Larger input capacitor values will improve ripple rejection further

improving the integrity of the output voltage.

Output Capacitance

Output bypass capacitors: Two (0.1µF and 1µF) ceramics and two 100µF low ESR tantalums

(AVX TPS or equivalent)

are required for loop stability. Faster transient performance can be

achieved with multiple additional 1µF ceramic capacitors. Ceramic capacitors greater than 1µF in

value are not recommended as they can cause stability issues.

Tantalum capacitor values larger than the suggested value are recommended to improve the

transient response under large load current changes. The upper capacitance value limit is

governed by the delayed over-current latch function of the regulator and

can be as much as

10,000µF without causing the device to latch-off during start-up.

General Layout Rules

Low impedance connections between the regulator output and load are essential. Solid power and

ground planes are highly recommended. In those cases where the board impedances are not kept

very small, oscillations can occur due to the effect of parasitic series resistance and inductance

on loop bandwidth and phase margin.

The V

SENSE

Pin must be connected directly to the

OUT

Pin using as short a trace as possible with

the connection inside the first bypass capacitor (see Fig. 2a).

Connect ceramic output capacitors directly across the V

OUT

and GND Pins with as wide a trace as

design rules allow (see Fig. 2a). Avoid the use of vias for these capacitors and avoid loops. Fig.2

shows the ceramic capacitors tied directly to the regulator output.

The input capacitors should be connected as close a possible to the V

Pin.

Fig. 2a.

Layer 1 conductor.

Ground plane below layer 1

Fig. 2b.

Layer 1 silkscreen

www.irf.com

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