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UT62L6416MC-70LE

Description
64K X 16 BIT LOW POWER CMOS SRAM
File Size190KB,12 Pages
ManufacturerETC
Download Datasheet View All

UT62L6416MC-70LE Overview

64K X 16 BIT LOW POWER CMOS SRAM

UTRON
Preliminary Rev. 0.1
64K X 16 BIT LOW POWER CMOS SRAM
GENERAL DESCRIPTION
The UT62L6416 is a 1,048,576-bit low power
CMOS static random access memory organized
as 65,536 words by 16 bits.
The UT62L6416 operates from a single 2.7V ~
3.6V power supply and all inputs and outputs are
fully TTL compatible.
The UT62L6416 is design for upper and low byte
access by data byte control( UB
LB
).
UT62L6416
FEATURES
Fast access time :
55ns(max) for Vcc=3.0V~3.6V
70/100ns(max) for Vcc=2.7V~3.6V
CMOS Low operating power
Operating current: 45/35/25mA (Icc max)
Standby current: 20 uA(TYP.) L-version
3 uA(TYP.) LL-version
Single 2.7V~3.6V power supply
Operating temperature:
Commercial : 0
~70
Extended : -20
~80
All inputs and outputs TTL compatible
Fully static operation
Three state outputs
Data retention voltage: 1.5V (min)
Data byte control :
LB
(I/O1~I/O8)
UB (I/O9~I/O16)
Package : 44-pin 400mil TSOP
48-pin 6mm × 8mm TFBGA
PIN DESCRIPTION
SYMBOL
A0 - A15
I/O1 - I/O16
CE
WE
OE
LB
UB
V
CC
V
SS
NC
VCC
VSS
DESCRIPTION
Address Inputs
Data Inputs/Outputs
Chip Enable Input
Write Enable Input
Output Enable Input
Lower-Byte Control
High-Byte Control
Power Supply
Ground
No Connection
FUNCTIONAL BLOCK DIAGRAM
A0
A1
A2
A3
A4
A8
A12
A13
A14
A15
I/O1
I/O16
I/O
ROW
DECODER
.
MEMORY ARRAY
.
.
1024 Rows x 64 Columns x 16 bits
.
.
.
.
.
.
CONTROL
.
.
.
.
.
.
COLUMN I/O
CE
WE
OE
COLUMN DECODER
LOGIC
CONTROL
LB
UB
A11 A10
A9
A7 A6 A5
UTRON TECHNOLOGY INC.
1F, No. 11, R&D Rd. II, Science-Based Industrial Park, Hsinchu, Taiwan, R. O. C.
TEL: 886-3-5777882
FAX: 886-3-5777919
P80073
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