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A500K270-FG676

Description
Field Programmable Gate Array, 26880-Cell, CMOS, PBGA676
CategoryProgrammable logic devices    Programmable logic   
File Size3MB,72 Pages
ManufacturerMicrosemi
Websitehttps://www.microsemi.com
Download Datasheet Parametric View All

A500K270-FG676 Overview

Field Programmable Gate Array, 26880-Cell, CMOS, PBGA676

A500K270-FG676 Parametric

Parameter NameAttribute value
Is it Rohs certified?incompatible
MakerMicrosemi
Reach Compliance Codeunknown
JESD-30 codeS-PBGA-B676
Number of entries440
Number of logical units26880
Output times440
Number of terminals676
Maximum operating temperature70 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeBGA
Encapsulate equivalent codeBGA676,26X26,40
Package shapeSQUARE
Package formGRID ARRAY
power supply2.5,2.5/3.3 V
Programmable logic typeFIELD PROGRAMMABLE GATE ARRAY
Certification statusNot Qualified
surface mountYES
technologyCMOS
Temperature levelCOMMERCIAL
Terminal formBALL
Terminal pitch1 mm
Terminal locationBOTTOM
Discontinued – v3.0
ProASIC
®
500K Family
F ea t u re s an d B e n e fi t s
H ig h C a p ac it y
I/O
• 100,000 to 475,000 System Gates
• 14k to 63k Bits of Two-Port SRAM
• 106 to 440 User I/Os
P e r f o r m an c e
• Mixed 2.5V/3.3V Support with Individually-Selectable
Voltage and Slew Rate
• 3.3V, PCI Compliance (PCI Revision 2.2)
S e c ur e P r o gr a m m in g
The Industry’s Most Effective Security Key Prevents Read
Back of Programming Bit Stream
S t a n da r d F P G A a nd A S I C D es ig n F lo w
• 33 MHz PCI 32-bit PCI
• Internal System Performance up to 250 MHz
• External System Performance up to 100 MHz
Lo w P ow e r
• Low Impedance Flash Switches
• Segmented Hierarchical Routing Structure
• Small, Efficient Logic Cells
H ig h P e r f o r m a nc e R o u t in g H ie r ar ch y
• Flexibility with Choice of Industry-Standard Front-End
Tools
• Efficient Design Through Front-End Timing and Gate
Optimization
I S P S u pp o r t
• In-System Programming (ISP) with Silicon Sculptor and
Flash Pro
S R A M s a nd F I F O s
Ultra Fast Local Network
Efficient Long Line Network
High Speed Very Long Line Network
High Performance Global Network
• Up to 150 MHz Synchronous and Asynchronous Operation
• Netlist Generator Ensures Optimal Usage of Embedded
Memory Blocks
B o u nd a r y S c an T e st
No nv o la t ile a n d Re pro g r am m a bl e Fl as h
T e c hn o log y
IEEE Std. 1149.1 (JTAG) Compliant
• Live at Power Up
• No Configuration Device Required
• Retains Programmed Design During Power-Down/
Power-Up Cycles
P ro A S I C P r o du c t P ro fi l e
Device
Maximum System Gates
Typical Gates
Maximum Flip-Flops
Embedded RAM Bits
Embedded RAM Blocks (256 X 9)
Logic Tiles
Global Routing Resources
Maximum User I/Os
JTAG
PCI
Package
(by Pin Count)
PQFP
PBGA
FBGA
A500K050
100,000
43,000
5,376
14k
6
5,376
4
204
Yes
Yes
208
272
144
A500K130
290,000
105,000
12,800
45k
20
12,800
4
306
Yes
Yes
208
272, 456
144, 256
A500K180
370,000
150,000
18,432
54k
24
18,432
4
362
Yes
Yes
208
456
256
A500K270
475,000
215,000
26,880
63k
28
26,880
4
440
Yes
Yes
208
456
256, 676
February 2002
1
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