CY2410SC-4 datasheet, PDF - EEWORLD Datasheet

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CY2410SC-4: DescriptionVideo Clock Generator, 27MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8; CategoryThe embedded processor and controller Microcontrollers and processors; File Size89KB，7 Pages; ManufacturerCypress Semiconductor

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CY2410SC-4 Overview

Video Clock Generator, 27MHz, CMOS, PDSO8, 0.150 INCH, SOIC-8

CY2410SC-4 Parametric

Parameter Name	Attribute value
Is it Rohs certified?	incompatible
Maker	Cypress Semiconductor
Parts packaging code	SOIC
package instruction	0.150 INCH, SOIC-8
Contacts	8
Reach Compliance Code	not_compliant
ECCN code	EAR99
JESD-30 code	R-PDSO-G8
JESD-609 code	e0
length	4.889 mm
Number of terminals	8
Maximum operating temperature	70 °C
Minimum operating temperature
Maximum output clock frequency	27 MHz
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	NOT SPECIFIED
power supply	3.3 V
Master clock/crystal nominal frequency	13.5 MHz
Certification status	Not Qualified
Maximum seat height	1.727 mm
Maximum slew rate	35 mA
Maximum supply voltage	3.465 V
Minimum supply voltage	3.135 V
Nominal supply voltage	3.3 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn/Pb)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	NOT SPECIFIED
width	3.9 mm
uPs/uCs/peripheral integrated circuit type	CLOCK GENERATOR, VIDEO

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CY2410

MPEG Clock Generator with VCXO

Features

• Integrated phase-locked loop (PLL)

• Low-jitter, high-accuracy outputs

• VCXO with analog adjust

• 3.3V operation

• Compatible with MK3727 (–1, –4, –5, –6, –7)

• Application compatibility for a wide variety of designs

• Enables design compatibility

• Advanced Features

• Serial programming interface (CY2410-3 only)

• Lower drive strength settings (CY2410-4, -6)

• Matches nonlinear MK3727A VCXO control curve (-5, -6)

• Matches nonlinear MK3727C VCXO control curve (-7)

Benefits

• Highest-performance PLL tailored for multimedia applica-

tions

• Meets critical timing requirements in complex system

designs

• Large ±150-ppm range, better linearity

Part

Number

CY2410–1

CY2410–3

CY2410–4

CY2410–5

CY2410–6

CY2410–7

Outputs

Input Frequency Range

Benefits

• Digital VCXO control

• Electromagnetic interference (EMI) reduction for standards

compliance

• Second source for existing designs

Output

Frequencies

VCXO Control

Curve

Other Features

Compatible with MK3727

Serial programming interface

Same as CY2410–1 except

lower drive strength settings

Matches MK3727A nonlinear

VCXO Control Curve

Same as CY2410–5 except

lower drive strength

Matches MK3727C nonlinear

VCXO control curve

13.5-MHz pullable crystal input per 1 copy of 27 MHz linear

Cypress specification

13.5-MHz pullable crystal input per 1 copy of 27 MHz linear

Cypress specification

13.5-MHz pullable crystal input per 1 copy of 27 MHz linear

Cypress specification

13.5-MHz pullable crystal input per 1 copy of 27 MHz nonlinear

Cypress specification

13.5-MHz pullable crystal input per 1 copy of 27 MHz nonlinear

Cypress specification

13.5-MHz pullable crystal input per 1 copy of 27 MHz nonlinear

Cypress specification

CY2410–1,–4,–5,–6,–7 Logic Block Diagram

13.5 XIN

XOUT

13.5 XIN

OSC

XOUT

VCO

VCXO

OUTPUT

DIVIDERS

27 MHz

CY2410–3 Logic Block Diagram

OSC

VCO

OUTPUT

DIVIDERS

27 MHz

PLL

SCLK

VDD

VSS

SDAT

Digital VCXO

Serial

Programming

Interface

VDD

VSS

Pin Configurations

CY2410–1,–4,–5,–6,–7

8-pin SOIC

XIN

VDD

VCXO

VSS

XOUT

NC or VSS

NC or VDD

27 MHz

XIN

VDD

SDAT

VSS

CY2410–3

8-pin SOIC

XOUT

NC or VSS

27 MHz

SCLK

Cypress Semiconductor Corporation

Document #: 38-07317 Rev. *D

•

3901 North First Street

•

San Jose

CA 95134

•

408-943-2600

Revised December 11, 2003

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