S71JL128HC0/128HB0/064HB0/
064HA0/064H80
Stacked Multi-Chip Product (MCP) Flash Memory
and pSRAM CMOS 3.0 Volt-only,
Simultaneous Operation Flash Memories and
Static RAM/Pseudo-static RAM
DISTINCTIVE CHARACTERISTICS
MCP Features
Operating Voltage Range of 2.7 to 3.3 V
High Performance
— Access time as fast as 55 ns
Packages
— 73-ball FBGA—8 x 11.6 mm
— 88-ball FBGA—8 x 11.6 mm
Operating Temperatures
— Wireless: –25°C to +85°C
— Industrial: –40°C to +85°C
PRELIMINARY
GENERAL DESCRIPTION
The S71JLxxxH Series is a product line of stacked Multi-Chip
Products (MCP) and consists of
One or more S29JL064H Flash devices
SRAM or pSRAM options
— 8Mb x 8/x 16 SRAM
— 16Mb x 16-only SRAM
— pSRAM x 16 only:
8Mb pSRAM
16Mb pSRAM
32Mb pSRAM
64Mb pSRAM
The products covered by this document are listed below. For
details about their specifications, please refer to the individual
constituent data sheets for further details.
MCP
S71JL064H80
S71JL064HA0
S71JL064HB0
S71JL128HB0
S71JL128HC0
Number of S29JL064H
1
1
1
2
2
Total Flash Density
64Mb
64Mb
64Mb
128Mb
128Mb
SRAM/pSRAM Density
8Mb
16Mb
32Mb
32Mb
64Mb
Notes:
1. This MCP is only guaranteed to operate @ 2.7 - 3.3 V regardless of component operating ranges.
2. BYTE# operation is only supported on the S71JL064H80xx0x.
Publication Number
S71JLxxxHxx_00
Revision
A
Amendment
3
Issue Date
May 25, 2004
P r e l i m i n a r y
Product Selector Guide
Device-Model #
S71JL064H80Bxx01
S71JL064H80Bxx02
S71JL064H80Bxx10
S71JL064H80Bxx11
S71JL064H80Bxx12
SRAM/pSRAM Density
8Mb
8Mb
8Mb
8Mb
8Mb
SRAM/pSRAM Type
SRAM - x8/x16
SRAM - x8/x16
pSRAM - x16
pSRAM - x16
pSRAM - x16
Supplier
Supplier 1
Supplier 1
Supplier 2
Supplier 2
Supplier 2
Flash Access RAM Access
Time (ns)
Time (ns)
70
85
55
70
85
70
85
55
70
85
Packages
FLB073
FLB073
FLJ073
FLJ073
FLJ073
S71JL064HA0Bxx01
S71JL064HA0Bxx02
S71JL064HA0Bxx10
S71JL064HA0Bxx11
S71JL064HA0Bxx12
S71JL064HA0Bxx62
16Mb
16Mb
16Mb
16Mb
16Mb
16Mb
SRAM - x16
SRAM - x16
pSRAM - x16
pSRAM - x16
pSRAM - x16
pSRAM - x16
Supplier 1
Supplier 1
Supplier 2
Supplier 2
Supplier 2
Supplier 4
70
85
55
70
85
70
70
85
55
70
85
70
FLB073
FLB073
FLJ073
FLJ073
FLJ073
FLJ073
S71JL128HB0Bxx01
S71JL128HB0Bxx02
32Mb
32Mb
pSRAM - x16
pSRAM - x16
Supplier 3
Supplier 3
70
85
70
85
FTA073
FTA073
S71JL128HC0Bxx01
S71JL128HC0Bxx02
64Mb
64Mb
pSRAM - x16
pSRAM - x16
Supplier 3
Supplier 3
70
85
70
85
FTA088
FTA088
2
S71JL128HC0/128HB0/064HB0/064HA0/064H80
S71JLxxxHxx_00A3 May 25, 2004
A d v a n c e
I n f o r m a t i o n
TABLE OF CONTENTS
S71JL128HC0/128HB0/064HB0/064HA0/064H80
Distinctive Characteristics . . . . . . . . . . . . . . . . . . . . 1
General Description . . . . . . . . . . . . . . . . . . . . . . . . . 1
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .2
Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
MCP Block Diagram of S71JL064H80, Model Numbers 01/02 ................7
MCP Block Diagram of S71JL064H80, Model Numbers 10/11/12 ..............7
MCP Block Diagram of S71JL064HA0, Model Numbers 01/02 ................8
MCP Block Diagram of S71JL064HA0, Model Numbers 10/11/12/62 .......8
MCP Block Diagram of S71JL064HB0, Model Numbers 00/01/02 ..........9
MCP Block Diagram of S71JL128HB0, Model Numbers 00/01/02 ......... 10
MCP Block Diagram of S71JL128HC0, Model Numbers 00/01/02 ......... 11
Accelerated Program Operation ................................................................. 8
Autoselect Functions ....................................................................................... 8
Simultaneous Read/Write Operations with Zero Latency ..................... 8
Standby Mode .........................................................................................................9
Automatic Sleep Mode ....................................................................................... 9
RESET#: Hardware Reset Pin ........................................................................... 9
Output Disable Mode ........................................................................................10
Table 2. S29JL064H Sector Architecture ............................... 11
Table 3. Bank Address ........................................................ 14
Table 4. SecSi
TM
Sector Addresses ....................................... 14
Autoselect Mode ................................................................................................. 14
Sector/Sector Block Protection and Unprotection .................................. 15
Table 5. S29JL064H Boot Sector/Sector Block Addresses for
Protection/Unprotection ...................................................... 15
Connection Diagrams . . . . . . . . . . . . . . . . . . . . . 12
Connection Diagram of S71JL064H80, Model Numbers 01/02 ............. 12
Special Package Handling Instructions .......................................................13
Pin Description .................................................................................................13
Logic Symbol .................................................................................................... 14
Connection Diagram of S71JL064H80, Model Numbers 10/11/12 ............15
Pin Description ................................................................................................ 16
Logic Symbol .................................................................................................... 16
Connection Diagram of S71JL064HA0, Model Numbers 01/02 ..............17
Pin Description ................................................................................................ 18
Logic Symbol .................................................................................................... 19
Connection Diagram of S71JL064HA0, Model Numbers 10/11/12/62 ... 20
Pin Description ................................................................................................ 21
Logic Symbol .................................................................................................... 21
Connection Diagram of S71JL064HB0, Model Numbers 00/01/02 ...... 22
Pin Description ................................................................................................23
Logic Symbol ....................................................................................................23
Connection Diagram of S71JL128HB0, Model Numbers 00/01/02 ....... 24
Pin Description ................................................................................................25
Logic Symbol ....................................................................................................25
Connection Diagram of S71JL128HC0, Model Numbers 00/01/02 ...... 26
Special Package Handling Instructions ..................................................... 26
Pin Description ................................................................................................27
Logic Symbol ....................................................................................................27
Look-ahead Connection Diagram ................................................................. 28
Write Protect (WP#) ........................................................................................ 17
Table 6. WP#/ACC Modes ................................................... 17
Temporary Sector Unprotect ......................................................................... 17
Figure 1. Temporary Sector Unprotect Operation ................... 18
Figure 2. In-System Sector Protect/Unprotect Algorithms ....... 19
SecSi™ (Secured Silicon) Sector
Flash Memory Region ........................................................................................20
Figure 3. SecSi Sector Protect Verify .................................... 21
Hardware Data Protection ..............................................................................21
Low VCC Write Inhibit ................................................................................. 21
Write Pulse “Glitch” Protection ............................................................... 22
Logical Inhibit ................................................................................................... 22
Power-Up Write Inhibit ............................................................................... 22
Common Flash Memory Interface (CFI) . . . . . . . 22
Table 1. CFI Query Identification String ................................
Table 7. System Interface String .........................................
Table 2. Device Geometry Definition ....................................
Table 3. Primary Vendor-Specific Extended Query..................
23
23
24
25
Command Definitions . . . . . . . . . . . . . . . . . . . . . . 26
Reading Array Data ........................................................................................... 26
Reset Command ................................................................................................. 26
Autoselect Command Sequence .................................................................... 27
Enter SecSi™ Sector/Exit SecSi Sector
Command Sequence .......................................................................................... 27
Byte/Word Program Command Sequence ................................................. 27
Unlock Bypass Command Sequence ........................................................28
Figure 4. Program Operation ............................................... 29
Ordering Information . . . . . . . . . . . . . . . . . . . . . . .30
Physical Dimensions . . . . . . . . . . . . . . . . . . . . . . . 34
FLB073 ....................................................................................................................34
FLJ073 ......................................................................................................................35
FTA073 ...................................................................................................................36
FTA088 ..................................................................................................................37
Chip Erase Command Sequence ................................................................... 29
Sector Erase Command Sequence ................................................................30
Figure 5. Erase Operation ................................................... 31
Erase Suspend/Erase Resume Commands ................................................... 31
Table 4. S29JL064H Command Definitions ............................ 33
S29JL064H
Write Operation Status . . . . . . . . . . . . . . . . . . . . . 34
DQ7: Data# Polling ............................................................................................ 34
Figure 6. Data# Polling Algorithm ........................................ 35
General Description 2
Product Selector Guide . . . . . . . . . . . . . . . . . . . . . .4
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
Logic Symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Device Bus Operations . . . . . . . . . . . . . . . . . . . . . . .6
Table 1. S29JL064H Device Bus Operations ............................ 6
RY/BY#: Ready/Busy# ........................................................................................36
DQ6: Toggle Bit I ............................................................................................... 36
Figure 7. Toggle Bit Algorithm ............................................. 37
Word/Byte Configuration .................................................................................. 7
Requirements for Reading Array Data ...........................................................7
Writing Commands/Command Sequences ...................................................7
DQ2: Toggle Bit II .............................................................................................. 37
Reading Toggle Bits DQ6/DQ2 ..................................................................... 38
DQ5: Exceeded Timing Limits ........................................................................ 38
DQ3: Sector Erase Timer ................................................................................ 38
Table 8. Write Operation Status ........................................... 39
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 40
Figure 8. Maximum Negative Overshoot Waveform ................ 40
Figure 9. Maximum Positive Overshoot Waveform.................. 40
May 25, 2004 S71JLxxxHxx_00A3
3
A d v a n c e
I n f o r m a t i o n
Operating Ranges . . . . . . . . . . . . . . . . . . . . . . . . . 40
Wireless (W) Devices .................................................................................. 40
Industrial (I) Devices ..................................................................................... 40
V
CC
Supply Voltages ..................................................................................... 40
8 Mb pSRAM (supplier 2)
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
General Description . . . . . . . . . . . . . . . . . . . . . . . 67
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Figure 34. Functional Block Diagram .................................... 68
Table 9. Functional Description ............................................ 68
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 41
CMOS Compatible ............................................................................................. 41
Zero-Power Flash ........................................................................................... 42
Figure 10. I
CC1
Current vs. Time (Showing Active and
Automatic Sleep Currents)................................................... 42
Figure 11. Typical I
CC1
vs. Frequency.................................... 42
Absolute Maximum Ratings (See Note) . . . . . . . 68
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 69
Operating Characteristics (Over Specified Temperature Range) .......69
Test Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure 12. Test Setup ........................................................ 43
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 10. Timing Test Conditions ......................................... 69
Table 11. Timings .............................................................. 70
Key To Switching Waveforms . . . . . . . . . . . . . . . .43
Figure 13. Input Waveforms and Measurement Levels............. 43
Timing Diagrams .................................................................................................. 71
Figure 35. Timing of Read Cycle (CE1# = OE# = V
IL
, WE# = CE2
= V
IH
).............................................................................. 71
Figure 36. Timing Waveform of Read Cycle (WE# = V
IH
) ........ 71
Figure 37. Timing Waveform of Write Cycle (WE# Control) ..... 72
Figure 38. Timing Waveform of Write Cycle (CE1# Control)..... 72
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .44
Read-Only Operations .................................................................................... 44
Figure 14. Read Operation Timings ....................................... 44
Hardware Reset (RESET#) ...............................................................................45
Figure 15. Reset Timings..................................................... 45
Word/Byte Configuration (BYTE#) ............................................................. 46
Figure 16. BYTE# Timings for Read Operations ...................... 47
Figure 17. BYTE# Timings for Write Operations ...................... 47
16 Mb pSRAM (supplier 2)
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73
General Description . . . . . . . . . . . . . . . . . . . . . . . 73
Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
Figure 39. Functional Block Diagram .................................... 74
Table 12. Functional Description .......................................... 74
Erase and Program Operations ..................................................................... 48
Figure 18. Program Operation Timings .................................. 49
Figure 19. Accelerated Program Timing Diagram .................... 49
Figure 20. Chip/Sector Erase Operation Timings ..................... 50
Figure 21. Back-to-back Read/Write Cycle Timings ................. 51
Figure 22. Data# Polling Timings (During Embedded Algorithms) .
51
Figure 23. Toggle Bit Timings (During Embedded Algorithms) .. 52
Figure 24. DQ2 vs. DQ6 ...................................................... 52
Absolute Maximum Ratings (See Note) . . . . . . . 75
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 75
Operating Characteristics (Over Specified Temperature Range) ....... 75
Temporary Sector Unprotect .........................................................................53
Figure 25. Temporary Sector Unprotect Timing Diagram.......... 53
Figure 26. Sector/Sector Block Protect and
Unprotect Timing Diagram................................................... 54
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 76
Timing Test Conditions .................................................................................... 76
Timings ................................................................................................................... 76
Timings ................................................................................................................... 77
Figure 40. Timing of Read Cycle (CE1# = OE# = V
IL
, WE# = CE2
= V
IH
).............................................................................. 77
Figure 41. Timing Waveform of Read Cycle (WE# = V
IH
) ........ 77
Figure 42. Timing Waveform of Write Cycle (WE# Control) ..... 78
Figure 43. Timing Waveform of Write Cycle (CE1# Control, CE2 =
High) ............................................................................... 78
Alternate CE# Controlled Erase and Program Operations ..................55
Figure 27. Alternate CE# Controlled Write (Erase/Program)
Operation Timings .............................................................. 56
Erase And Programming Performance . . . . . . . . 57
16 Mb SRAM (supplier 1)
Functional Description . . . . . . . . . . . . . . . . . . . . . 59
Absolute Maximum Ratings . . . . . . . . . . . . . . . . . 59
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 60
Recommended DC Operating Conditions (Note 1) ............................... 60
Capacitance (f=1MHz, T
A
=25°C) ................................................................... 60
DC Operating Characteristics ....................................................................... 60
16 Mb pSRAM (supplier 4)
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maxumum Ratings (see Note) . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .
79
79
79
80
80
80
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 61
Read/Write Charcteristics (V
CC
=2.7-3.3V) ................................................. 61
Data Retention Characteristics ...................................................................... 61
Timing Diagrams ................................................................................................. 62
Figure 28. Timing Waveform of Read Cycle(1) (address controlled,
CD#1=OE#=V
IL
, CS2=WE#=V
IH
, UB# and/or LB#=V
IL
)......... 62
Figure 29. Timing Waveform of Read Cycle(2) (WE#=V
IH
)....... 62
Figure 30. Timing Waveform of Write Cycle(1) (WE# controlled) ..
63
Figure 31. Timing Waveform of Write Cycle(2) (CS# controlled) ...
63
Figure 32. Timing Waveform of Write Cycle(3) (UB#, LB#
controlled) ........................................................................ 64
Figure 33. Data Retention Waveform .................................... 65
Table 13. DC Recommended Operating Conditions ................. 80
Table 14. DC Characteristics (T
A
= -25°C to 85°C, VDD = 2.6 to
3.3V) ............................................................................... 81
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 81
Table 15. AC Characteristics and Operating Conditions (T
A
= -25°C
to 85°C, V
DD
= 2.6 to 3.3V) ................................................ 81
Table 16. AC Test Conditions ............................................... 82
Figure 44. AC Test Loads .................................................... 82
Figure 45. State Diagram ................................................... 83
Table 17. Standby Mode Characteristics ................................ 83
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 83
Figure 46. Read Cycle 1—Addressed Controlled ..................... 83
Figure 47. Read Cycle 2—CS1# Controlled............................ 84
4
S71JLxxxHxx_00A3 May 25, 2004
A d v a n c e
I n f o r m a t i o n
Figure 48. Write Cycle 1—WE# Controlled ............................. 84
Figure 49. Write Cycle 2—CS1# Controlled ............................ 85
Figure 50. Write Cycle3—UB#, LB# Controlled ....................... 85
Figure 51. Deep Power-down Mode....................................... 86
Figure 52. Power-up Mode................................................... 86
Figure 53. Abnormal Timing................................................. 86
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 99
3.3V) ............................................................................... 99
Table 25. Capacitance (T
A
= 25°C, f = 1 MHz) ....................... 99
Table 26. AC Characteristics and Operating Conditions (T
A
= -25°C
to 85°C, V
DD
= 2.6 to 3.3V) ................................................ 99
Table 27. AC Test Conditions ............................................. 100
32 Mb pSRAM (Supplier 3)
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maxumum Ratings . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .
87
87
87
88
88
88
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 62. Read Cycle ......................................................
Figure 63. Page Read Cycle (8 words access) ......................
Figure 64. Write Cycle 1 (WE# controlled) ..........................
Figure 65. Write Cycle 2 (CE# controlled) ...........................
Figure 66. Deep Power-down Timing ..................................
Figure 67. Power-on Timing ..............................................
Figure 68. Read Address Skew Provisions ...........................
Figure 69. Write Address Skew Provisions ...........................
101
102
103
104
104
104
105
105
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 18. DC Recommended Operating Conditions (T
A
= -40°C to
85°C) ............................................................................... 88
Table 19. DC Characteristics (T
A
= -40°C to 85°C, VDD = 2.6 to
3.3V) ............................................................................... 89
Table 20. Capacitance (T
A
= 25°C, f = 1 MHz) ....................... 89
Table 21. AC Characteristics and Operating Conditions (T
A
= -40°C
to 85°C, V
DD
= 2.6 to 3.3V) ................................................ 89
Table 22. AC Test Conditions .............................................. 90
8 Mb SRAM (supplier 1)
Functional Description . . . . . . . . . . . . . . . . . . . . . 107
Table 28. Word Mode ....................................................... 107
Table 29. Byte Mode ........................................................ 107
Absolute Maximum Ratings . . . . . . . . . . . . . . . 108
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . 108
Recommended DC Operating Conditions ............................................... 108
Capacitance (f=1MHz, T
A
=25°C) ................................................................. 108
DC and Operating Characteristics ............................................................. 109
Timing Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . 91
Figure 54. Read Cycle ......................................................... 91
Figure 55. Page Read Cycle (8 words access)......................... 92
Figure 56. Write Cycle 1 (WE# controlled) ............................. 93
Figure 57. Write Cycle 2 (CE# controlled).............................. 94
Figure 58. Deep Power-down Timing..................................... 94
Figure 59. Power-on Timing................................................. 94
Figure 60. Read Address Skew Provisions .............................. 95
Figure 61. Write Address Skew Provisions.............................. 95
AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 110
Read/Write Charcteristics (V
CC
=2.7-3.3V) ................................................110
Data Retention Characteristics .....................................................................110
Timing Diagrams ..................................................................................................111
Figure 70. Timing Waveform of Read Cycle(1) (address controlled,
CD#1=OE#=V
IL
, CS2=WE#=V
IH
, UB# and/or LB#=V
IL
) ...... 111
Figure 71. Timing Waveform of Read Cycle(2) (WE#=V
IH
, if BYTE#
is low, ignore UB#/LB# timing) ......................................... 111
Figure 72. Timing Waveform of Write Cycle(1) (WE# controlled, if
BYTE# is low, ignore UB#/LB# timing)............................... 111
Figure 73. Timing Waveform of Write Cycle(2) (CE1# controlled, if
BYTE# is low, ignore UB#/LB# timing)............................... 112
Figure 74. Timing Waveform of Write Cycle(3) (UB#, LB#
controlled, BYTE# must be high) ....................................... 112
64 Mb pSRAM (supplier 3)
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . .
Operation Mode . . . . . . . . . . . . . . . . . . . . . . . . . .
Absolute Maxumum Ratings . . . . . . . . . . . . . . . .
DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . .
97
97
97
98
98
98
Data Retention Waveforms ............................................................................113
Figure 75. CE1# Controlled............................................... 113
Figure 76. CS2 Controlled ................................................. 113
Table 23. DC Recommended Operating Conditions (T
A
= -25°C to
85°C) ............................................................................... 98
Table 24. DC Characteristics (T
A
= -25°C to 85°C, VDD = 2.6 to
Revision Summary
May 25, 2004 S71JLxxxHxx_00A3
5
Embedded System
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