MPC8545VUANG datasheet, PDF - EEWORLD Datasheet

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MPC8545VUANG: Description32-BIT, 800MHz, MICROPROCESSOR, CBGA783, 29 X 29 MM, 1 MM PITCH, LEAD FREE, CERAMIC, FCBGA-783; CategoryThe embedded processor and controller Microcontrollers and processors; File Size1MB，144 Pages; ManufacturerNXP; Websitehttps://www.nxp.com; Environmental Compliance

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MPC8545VUANG Overview

32-BIT, 800MHz, MICROPROCESSOR, CBGA783, 29 X 29 MM, 1 MM PITCH, LEAD FREE, CERAMIC, FCBGA-783

MPC8545VUANG Parametric

Parameter Name	Attribute value
Is it Rohs certified?	conform to
Maker	NXP
Parts packaging code	BGA
package instruction	29 X 29 MM, 1 MM PITCH, LEAD FREE, CERAMIC, FCBGA-783
Contacts	783
Reach Compliance Code	not_compliant
ECCN code	5A992
Address bus width	64
bit size	32
boundary scan	YES
maximum clock frequency	133 MHz
External data bus width	64
Format	FLOATING POINT
Integrated cache	YES
JESD-30 code	S-CBGA-B783
JESD-609 code	e2
length	29 mm
low power mode	YES
Humidity sensitivity level	1
Number of terminals	783
Package body material	CERAMIC, METAL-SEALED COFIRED
encapsulated code	BGA
Encapsulate equivalent code	BGA783,28X28,40
Package shape	SQUARE
Package form	GRID ARRAY
Peak Reflow Temperature (Celsius)	260
power supply	1.2,2.5/3.3 V
Certification status	Not Qualified
Maximum seat height	3.38 mm
speed	800 MHz
Maximum supply voltage	1.155 V
Minimum supply voltage	1.045 V
Nominal supply voltage	1.1 V
surface mount	YES
technology	CMOS
Terminal surface	Tin/Silver (Sn/Ag)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	40
width	29 mm
uPs/uCs/peripheral integrated circuit type	MICROPROCESSOR

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Freescale Semiconductor

Technical Data

Document Number: MPC8548EEC

Rev. 6, 12/2009

MPC8548E PowerQUICC™ III

Integrated Processor

Hardware Specifications

Overview

Contents

Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . 10

Power Characteristics . . . . . . . . . . . . . . . . . . . . . . . . 14

Input Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

RESET Initialization . . . . . . . . . . . . . . . . . . . . . . . . . 18

DDR and DDR2 SDRAM . . . . . . . . . . . . . . . . . . . . . 19

DUART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25

Enhanced Three-Speed Ethernet (eTSEC) . . . . . . . . 26

Ethernet Management Interface Electrical

Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39

Local Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41

Programmable Interrupt Controller . . . . . . . . . . . . . 51

JTAG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51

C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54

PCI/PCI-X . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56

High-Speed Serial Interfaces (HSSI) . . . . . . . . . . . . 60

PCI Express . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68

Serial RapidIO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77

Package Description . . . . . . . . . . . . . . . . . . . . . . . . . 87

Clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123

Thermal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127

System Design Information . . . . . . . . . . . . . . . . . . 128

Ordering Information . . . . . . . . . . . . . . . . . . . . . . . 137

Document Revision History . . . . . . . . . . . . . . . . . . 141

This section provides a high-level overview of MPC8548E

features.

Figure 1

shows the major functional units within

the MPC8548E.

Although this document is written from the perspective of

the MPC8548E, most of the material applies to the other

family members—MPC8547E, MPC8545E, and

MPC8543E—as well. When specific differences occur, such

as pinout differences and processor frequency ranges, they

will be identified as such.

For specific PVR and SVR numbers, refer to the

MPC8548E

PowerQUICC™ III Integrated Processor Family Reference

Manual.

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