32MB, 64MB (x32, SR)
100-PIN DDR UDIMM
DDR SDRAM
UNBUFFERED DIMM
Features
• 100-pin, dual in-line memory module (DIMM)
• Fast data transfer rate PC2100 and PC2700
• Utilizes 266 MT/s or 333 MT/s DDR SDRAM
components
• 32MB (8 Meg x 32) and 64MB (16 Meg x 32)
• V
DD
= V
DD
Q = +2.5V
• 2.5V I/O (SSTL_2 compatible)
• Commands entered on each positive CK edge
• DQS edge-aligned with data for READs; center-
aligned with data for WRITEs
• Internal, pipelined double data rate (DDR)
architecture; two data accesses per clock cycle
• Bidirectional data strobe (DQS) transmitted/
received with data—i.e., source-synchronous data
capture
• Differential clock inputs CK and CK#
• Four internal device banks for concurrent operation
• Programmable burst lengths: 2, 4, or 8
• Auto precharge option
• Serial Presence Detect (SPD) with EEPROM
• Programmable READ CAS latency
• Auto Refresh and Self Refresh Modes
15.625µs (32MB), 7.8125µs (64MB) maximum
average periodic refresh interval
• Gold edge contacts
MT2VDDT832U –
32MB
MT2VDDT1632U –
64MB
For the latest data sheet, please refer to the Micron
Web
site:
www.micron.com/products/modules
Figure 1:
100-Pin DIMM (MO-161)
OPTIONS
MARKING
G
Y
none
I
-6
-75Z
1
-75
• Package
100-pin DIMM (standard)
100-pin DIMM (lead-free)
1
• Operating Temperature Range
Commercial (ambient)
Industrial (ambient)
• Frequency/CAS Latency
2
6ns/167 MHz (333 MT/s) CL = 2.5
7.5ns/133 MHz (266 MT/s) CL = 2
7.5ns/133 MHz (266 MT/s) CL = 2.5
NOTE:
2. CL = CAS (READ) latency.
1. Contact Micron for product availability.
Table 1:
Address Table
MT2VDDT832U
MT2VDDT1632U
8K
8K (A0–A12)
4 (BA0, BA1)
256Mb (16 Meg x 16)
512 (A0–A8)
1 (S0#)
4K
4K (A0–A11)
4 (BA0, BA1)
128Mb (8 Meg x 16)
512 (A0–A8)
1 (S0#)
Refresh Count
Row Addressing
Device Bank Addressing
Device Configuration
Column Addressing
Module Rank Addressing
pdf: 09005aef808ebdbc, source: 09005aef808e914b
DD2C8_16x32UG.fm - Rev. D 9/04 EN
1
©2004 Micron Technology, Inc. All rights reserved.
PRODUCTS AND SPECIFICATIONS DISCUSSED HEREIN ARE SUBJECT TO CHANGE BY MICRON WITHOUT NOTICE.
32MB, 64MB (x32, SR)
100-PIN DDR UDIMM
Table 2:
Part Numbers and Timing Parameters
MODULE
DENSITY
32MB
32MB
32MB
32MB
32MB
32MB
64MB
64MB
64MB
64MB
64MB
64MB
CONFIGURATION
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
8 Meg x 32
16 Meg x 32
16 Meg x 32
16 Meg x 32
16 Meg x 32
16 Meg x 32
16 Meg x 32
LATENCY
MODULE
MEMORY CLOCK/
BANDWIDTH
DATA BIT RATE
(CL -
t
RCD -
t
RP)
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.7 GB/s
2.7 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
2.1 GB/s
6ns/333 MT/s
6ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
6ns/333 MT/s
6ns/333 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
7.5ns/266 MT/s
2.5-3-3
2.5-3-3
2-3-3
2-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2.5-3-3
2-3-3
2-3-3
2.5-3-3
2.5-3-3
PART NUMBER
MT2VDDT832UG-6__
MT2VDDT832UY-6__
MT2VDDT832UG-75Z__
MT2VDDT832UY-75Z__
MT2VDDT832UG-75__
MT2VDDT832UY-75__
MT2VDDT1632UG-6__
MT2VDDT1632UY-6__
MT2VDDT1632UG-75Z__
MT2VDDT1632UY-75Z__
MT2VDDT1632UG-75__
MT2VDDT1632UY-75__
NOTE:
All part numbers end with a two-place code (not shown), designating component and PCB revisions. Consult factory for
current revision codes. Example: MT2VDDT832UG-75B1.
pdf: 09005aef808ebdbc, source: 09005aef808e914b
DD2C8_16x32UG.fm - Rev. D 9/04 EN
2
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
32MB, 64MB (x32, SR)
100-PIN DDR UDIMM
Table 3:
Pin Assignment
(100-Pin DIMM Front)
14
15
16
17
18
19
20
21
22
23
24
25
V
DD
DQ11
V
SS
CK0
CK0#
V
DD
NC
NC/A12
NC
A9
A7
V
SS
26
27
28
29
30
31
32
33
34
35
36
37
38
A5
A3
A1
A10
V
DD
BA0
WE#
S0#
DQ16
V
SS
DQ17
DQS2
V
DD
39
40
41
42
43
44
45
46
47
48
49
50
DQ18
DQ19
V
DD
DQ24
DQ25
V
SS
DQS3
DQ26
V
SS
DQ27
SA0
V
REF
Table 4:
Pin Assignment
(100-Pin DIMM Back)
64
65
66
67
68
69
70
71
72
73
74
75
V
DD
DQ15
V
SS
DNU
DNU
V
DD
CKE0
A11
A8
A6
A4
V
SS
76
77
78
79
80
81
82
83
84
85
86
87
88
A2
A0
BA1
RAS#
V
DD
CAS#
NC
DNU
DQ20
V
SS
DQ21
DM2
V
DD
89
90
91
92
93
94
95
96
97
98
99
100
DQ22
DQ23
V
DD
DQ28
DQ29
V
SS
DM3
DQ30
V
SS
DQ31
SDA
SCL
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
1
2
3
4
5
6
7
8
9
10
11
12
13
NOTE:
PIN SYMBOL PIN SYMBOL PIN SYMBOL PIN SYMBOL
51
52
53
54
55
56
57
58
59
60
61
62
63
DQ4
V
SS
DQ5
DM0
V
DD
DQ6
DQ7
V
DD
DQ12
DQ13
V
SS
DM1
DQ14
DQ0
V
SS
DQ1
DQS0
V
DD
DQ2
DQ3
V
DD
DQ8
DQ9
V
SS
DQS1
DQ10
Pin 21 is No Connect for the 32MB module, or A12 for the 64MB module.
Figure 2: Module Layout
Front View
U1
U2
U3
Back View
No Components on This Side of Module
PIN 1
PIN 23
PIN 50
PIN100
PIN 73
PIN 51
Indicates a V
DD
or V
DD
Q
pin
Indicates a V
SS
pin
pdf: 09005aef808ebdbc, source: 09005aef808e914b
DD2C8_16x32UG.fm - Rev. D 9/04 EN
3
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
32MB, 64MB (x32, SR)
100-PIN DDR UDIMM
Table 5:
Pin Descriptions
SYMBOL
WE#, CAS#, RAS#
CK0, CK0#
TYPE
Input
Input
DESCRIPTION
Command Inputs: RAS#, CAS#, and WE# (along with S#) define
the command being entered.
Clock: CK, CK# are differential clock inputs. All address and
control input signals are sampled on the crossing of the
positive edge of CK,and negative edge of CK#. Output data
(DQ and DQS) is referenced to the crossings of CK and CK#.
Clock Enable: CKE HIGH activates and CKE LOW deactivates
the internal clock, input buffers and output drivers. Taking
CKE LOW provides PRECHARGE POWER-DOWN and SELF
REFRESH operations (all device banks idle), or ACTIVE POWER-
DOWN (row ACTIVE in any device bank).CKE is synchronous
for POWER-DOWN entry and exit, and for SELF REFRESH entry.
CKE is asynchronous for SELF REFRESH exit and for disabling
the outputs. CKE must be maintained HIGH throughout read
and write accesses. Input buffers (excluding CK, CK#, and CKE)
are disabled during POWER-DOWN. Input buffers (excluding
CKE) are disabled during SELF REFRESH. CKE is an SSTL_2 input
but will detect an LVCMOS LOW level after V
DD
is applied.
Chip Selects: S# enables (registered LOW) and disables
(registered HIGH) the command decoder. All commands are
masked when S# is registered HIGH. S# is considered part of
the command code.
Bank Address: BA0 and BA1 define to which device bank an
ACTIVE, READ, WRITE, or PRECHARGE command is being
applied.
Address Inputs: Provide the row address for ACTIVE
commands, and the column address and auto precharge bit
(A10) for READ/WRITE commands, to select one location out
of the memory array in the respective device bank. A10
sampled during a PRECHARGE command determines whether
the PRECHARGE applies to one device bank (A10 LOW, device
bank selected by BA0, BA1) or all device banks (A10 HIGH).
The address inputs also provide the op-code during a MODE
REGISTER SET command. BA0 and BA1 define which mode
register (mode register or extended mode register) is loaded
during the LOAD MODE REGISTER command.
Data Strobe: Output with READ data, input with WRITE data.
DQS is edge-aligned with READ data, centered in WRITE data.
Used to capture data.
Data Write Mask. DM LOW allows WRITE operation. DM HIGH
blocks WRITE operation. DM lines do not affect READ
operation.
Data I/Os: Data bus.
Refer to Pin Assignment Tables on page 3 for pin number and symbol information
PIN NUMBERS
32, 79, 81
17, 18
70
CKE0
Input
33
S0#
Input
31, 78
BA0, BA1
Input
21
(64MB),
23, 24, 26-29, 71–
74, 76, 77
A0–A11
(32MB)
A0–A12
(64MB)
Input
4, 12, 37, 45
DQS0–DQS3
Input/
Output
Input
54, 62, 87, 95
DM0–DM3
1, 3, 6, 7, 9,10, 13, 15, 34, 36,
39, 40, 42, 43, 46, 48, 51, 53,
56, 57, 59, 60, 63, 65, 84, 86,
89, 90, 92, 93, 96, 98
49
99
DQ0–DQ31
Input/
Output
SA0
SDA
Input
Input/
Output
Presence-Detect Address Inputs: These pins are used to
configure the presence-detect device.
Serial Presence-Detect Data: SDA is a bidirectional pin used to
transfer addresses and data into and out of the presence-
detect portion of the module.
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
pdf: 09005aef808ebdbc, source: 09005aef808e914b
DD2C8_16x32UG.fm - Rev. D 9/04 EN
4
32MB, 64MB (x32, SR)
100-PIN DDR UDIMM
Table 5:
Pin Descriptions (Continued)
SYMBOL
SCL
V
REF
V
DD
V
SS
DNU
NC
TYPE
Input
Supply
Supply
Supply
—
—
DESCRIPTION
Serial Clock for Presence-Detect: SCL is used to synchronize the
presence-detect data transfer to and from the module.
SSTL_2 reference voltage.
Power Supply: +2.5V ±0.2V.
Ground.
Do Not Use: This pin is not connected on these modules, but is
an assigned pin on other modules in this product family.
No Connect: These pins should be left unconnected.
Refer to Pin Assignment Tables on page 3 for pin number and symbol information
PIN NUMBERS
100
50
5, 8, 14, 19, 30, 38, 41, 55,
58, 64, 69, 80, 88, 91
2, 11, 16, 25, 35, 44, 47, 52,
61, 66, 75, 85, 94, 97
67, 68, 83
20, 21 (32MB), 22, 82
pdf: 09005aef808ebdbc, source: 09005aef808e914b
DD2C8_16x32UG.fm - Rev. D 9/04 EN
5
Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2004 Micron Technology, Inc. All rights reserved.
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