S29AL032D
32 Mbit, 3 V, Flash 4 M x 8-Bit Uniform
Sector 4 M x 8-Bit/2 M x 16-Bit Boot Sector
This product has been retired and is not recommended for designs. For new and current designs, the S29GL064S supersedes the
S29AL032D. This is the factory-recommended migration path. Please refer to the S29GL064S data sheet for specifications and
ordering information. Availability of this document is retained for reference and historical purposes only.
Distinctive Characteristics
Architectural Advantages
Single power supply operation
– Full voltage range: 2.7 to 3.6 volt read and write operations for
battery-powered applications
Manufactured on 200-nm process technology
– Fully compatible with 0.23 µm Am29LV320D, 0.32 µm
Am29LV033C, and 0.33 µm MBM29LV320E devices
Flexible sector architecture
– Boot sector models: Eight 8-Kbyte sectors; sixty-three 64-Kbyte
sectors; top or bottom boot block configurations available
– Uniform sector models: Sixty-four 64-Kbyte sectors
Sector Protection features
– A hardware method of locking a sector to prevent any program or
erase operations within that sector
– Sectors can be locked in-system or via programming equipment
– Temporary Sector Unprotect feature allows code changes in
previously locked sectors
Unlock Bypass Program Command
– Reduces overall programming time when issuing multiple program
command sequences
Performance Characteristics
High performance
– Access times as fast as 70 ns
Ultra low power consumption (typical values at 5 MHz)
– 200 nA Automatic Sleep mode current
– 200 nA standby mode current
– 9 mA read current
– 20 mA program/erase current
Data retention: 20 years typical
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Compatibility with JEDEC standards
– Pinout and software compatible with single-power supply Flash
– Superior inadvertent write protection
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Secured Silicon Sector
– 128-word sector for permanent, secure identification through an 8-
word random Electronic Serial Number
– May be programmed and locked at the factory or by the customer
– Accessible through a command sequence
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Package Options
48-ball FBGA
48-pin TSOP
40-pin TSOP
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Erase Suspend/Erase Resume
– Suspends an erase operation to read data from, or program data
to, a sector that is not being erased, then resumes the erase
operation
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Data# Polling and toggle bits
– Provides a software method of detecting program or erase
operation completion
– Unlock Bypass Program Command
Reduces overall programming time when issuing multiple program
command sequences
Hardware Features
Ready/Busy# pin (RY/BY#)
– Provides a hardware method of detecting program or erase cycle
completion
Hardware reset pin (RESET#)
– Hardware method to reset the device to reading array data
WP#/ACC input pin
– Write protect (WP#) function allows protection of two outermost
boot sectors (boot sector models only), regardless of sector
protect status
– Acceleration (ACC) function provides accelerated program times
Cypress Semiconductor Corporation
Document Number: 002-02003 Rev. *B
•
198 Champion Court
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CFI (Common Flash Interface) compliant
– Provides device-specific information to the system, allowing host
software to easily reconfigure for different Flash devices
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Software Features
San Jose
,
CA 95134-1709
•
408-943-2600
Revised January 08, 2016
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Cycling endurance: 1,000,000 cycles per sector typical
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S29AL032D
General Description
The S29AL032D is a 32-megabit, 3.0 volt-only flash memory device, organized as 2,097,152 words of 16 bits each or 4,194,304
bytes of 8 bits each. Word mode data appears on DQ0-DQ15; byte mode data appears on DQ0-DQ7. The device is designed to
be programmed in-system with the standard 3.0 volt VCC supply, and can also be programmed in standard EPROM
programmers.
The device is available with access times as fast as 70 ns. The devices are offered in 40-pin TSOP, 48-pin TSOP and 48-ball
FBGA packages. Standard control pins- chip enable (CE#), write enable (WE#), and output enable (OE#)-control normal read
and write operations, and avoid bus contention issues.
The device requires only a
single 3.0 volt power supply
for both read and write functions. Internally generated and regulated
voltages are provided for the pro-gram and erase operations.
S29AL032D Features
Device erasure occurs by executing the erase command sequence. This initiates the
Embedded Erase
algorithm—an internal
algorithm that automatically preprograms the array (if it is not already programmed) before executing the erase operation. During
erase, the device automatically times the erase pulse widths and verifies proper cell margin.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin, or by reading the
DQ7 (Data# Polling) and DQ6 (toggle)
status bits.
After a program or erase cycle has been completed, the device is ready to
read array data or accept another command.
The
sector erase architecture
allows memory sectors to be erased and reprogrammed without affecting the data contents of
other sectors. The device is fully erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations during power
transitions. The
hardware sector protection
feature disables both program and erase operations in any combination of the
sectors of memory. This can be achieved in-system or via programming equipment.
The
Erase Suspend/Erase Resume
feature enables the user to put erase on hold for any period of time to read data from, or
program data to, any sector that is not selected for erasure. True background erase can thus be achieved.
The
hardware RESET# pin
terminates any operation in progress and resets the internal state machine to reading array data. The
RESET# pin may be tied to the system reset circuitry. A system reset would thus also reset the device, enabling the system
microprocessor to read the boot-up firmware from the Flash memory.
The device offers two power-saving features. When addresses are stable for a specified amount of time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby mode.
Power consumption is greatly reduced in
both these modes.
The Spansion Flash technology combines years of Flash memory manufacturing experience to produce the highest levels of
quality, reliability and cost effectiveness. The device electrically erases all bits within a sector simultaneously via
Fowler-Nordheim tunneling. The data is programmed using hot-electron injection.
Document Number: 002-02003 Rev. *B
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Device programming occurs by executing the program command sequence. This initiates the
Embedded Program
algorithm—
an internal algorithm that automatically times the program pulse widths and verifies proper cell margin. The
Unlock Bypass
mode facilitates faster programming times by requiring only two write cycles to program data instead of four.
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The S29AL032D is entirely command set compatible with the
JEDEC single-power-supply Flash standard.
Commands are
written to the command register using standard microprocessor write timings. Register contents serve as input to an internal
state-machine that controls the erase and programming circuitry. Write cycles also internally latch addresses and data needed for
the programming and erase operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
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Factory locked parts provide several options. The Secured Silicon Sector may store a secure, random 16 byte ESN (Electronic
Serial Number), customer code (programmed through the Spansion programming service), or both.
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The
Secured Silicon Sector
is an extra sector capable of being permanently locked by Spansion or customers. The
Secured
Silicon Indicator Bit
(DQ7) is permanently set to a 1 if the part is
factory locked,
and set to a 0 if customer lockable. This way,
customer lockable parts can never be used to replace a factory locked part.
Note that the S29AL032D has a Secured Silicon
Sector size of 128 words (256 bytes).
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Page 2 of 64
S29AL032D
Contents
1.
2.
3.
3.1
3.2
3.3
4.
5.
6.
6.1
6.2
7.
7.1
7.2
7.3
7.4
7.5
7.6
7.7
7.8
7.9
7.10
7.11
7.12
7.13
7.14
8.
8.1
8.2
9.
9.1
9.2
9.3
9.4
10.
11.
11.1
11.2
11.3
11.4
Product Selector Guide
............................................... 4
Block Diagram..............................................................
4
Connection Diagrams..................................................
FBGA Package for Model 00 Only.................................
FBGA Package for Models 03, 04 Only .........................
Special Handling Instructions.........................................
5
6
7
7
12.
12.1
12.2
12.3
12.4
12.5
12.6
12.7
13.
14.
Write Operation Status
............................................... 37
DQ7: Data# Polling ....................................................... 37
RY/BY#: Ready/Busy#.................................................. 38
DQ6: Toggle Bit I .......................................................... 39
DQ2: Toggle Bit II ......................................................... 39
Reading Toggle Bits DQ6/DQ2..................................... 39
DQ5: Exceeded Timing Limits ...................................... 40
DQ3: Sector Erase Timer.............................................. 41
Absolute Maximum Ratings.......................................
42
Operating Ranges
....................................................... 43
Pin Configuration.........................................................
7
Logic Symbols
............................................................. 8
Ordering Information
................................................... 9
S29AL032D Standard Products..................................... 9
Valid Combinations ...................................................... 10
Device Bus Operations..............................................
Word/Byte Configuration (Models 03, 04 Only) ...........
Requirements for Reading Array Data.........................
Writing Commands/Command Sequences..................
Program and Erase Operation Status..........................
Accelerated Program Operation ..................................
Standby Mode..............................................................
Automatic Sleep Mode.................................................
RESET#: Hardware Reset Pin.....................................
Output Disable Mode ...................................................
Sector Addresss Tables...............................................
Autoselect Mode ..........................................................
Sector Protection/Unprotection ....................................
Write Protect (WP#) — Models 03, 04 Only ................
Temporary Sector Unprotect........................................
10
10
11
11
11
11
11
12
12
13
13
19
20
24
24
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Hardware Data Protection
.........................................
Low V
CC
Write Inhibit...................................................
Write Pulse “Glitch” Protection.....................................
Logical Inhibit ...............................................................
Power-Up Write Inhibit .................................................
R
Secured Silicon Sector Flash Memory Region
....... 24
Factory Locked: Secured Silicon Sector Programmed
and Protected at the Factory ........................................ 25
Customer Lockable: Secured Silicon Sector NOT
Programmed or Protected at the Factory..................... 25
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26
26
26
26
26
Common Flash Memory Interface (CFI)
................... 27
Command Definitions................................................
29
Reading Array Data ..................................................... 29
Reset Command .......................................................... 29
Autoselect Command Sequence ................................. 30
Enter Secured Silicon Sector/Exit Secured Silicon Sector
Command Sequence ................................................... 30
11.5 Word/Byte Program Command Sequence................... 30
11.6 Unlock Bypass Command Sequence .......................... 30
11.7 Chip Erase Command Sequence ................................ 31
11.8 Sector Erase Command Sequence ............................. 32
11.9 Erase Suspend/Erase Resume Commands ................ 32
11.10Command Definitions Table ........................................ 34
Document Number: 002-02003 Rev. *B
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18.
19.
19.1
19.2
19.3
20.
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17.
17.1
17.2
17.3
AC Characteristics......................................................
47
Read Operations........................................................... 47
Hardware Reset (RESET#)........................................... 48
Word/Byte Configuration (BYTE#)
(Models 03, 04 Only)......................................................49
17.4 Erase/Program Operations ........................................... 50
17.5 Temporary Sector Unprotect......................................... 53
17.6 Alternate CE# Controlled Erase/Program Operations .. 55
Erase and Programming Performance
..................... 57
TSOP and BGA Pin Capacitance
............................... 57
TS040—40-Pin Standard TSOP................................... 58
TS 048—48-Pin Standard TSOP .................................. 60
VBN048—48-Ball Fine-Pitch Ball Grid Array (FBGA)
10.0 x 6.0 mm ...............................................................61
Document History Page
............................................. 62
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16. Test Conditions
........................................................... 46
16.1 Key to Switching Waveforms ........................................ 46
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15. DC Characteristics......................................................
44
15.1 Zero Power Flash.......................................................... 45
Page 3 of 64
S29AL032D
1.
Product Selector Guide
S29AL032D
Voltage Range: V
CC
= 2.7–3.6 V
70
70
70
30
90
90
90
35
Family Part Number
Speed Option
Max access time, ns (t
ACC
)
Max CE# access time, ns (t
CE
)
Max OE# access time, ns (t
OE
)
Note
See
AC Characteristics on page 47
for full specifications.
2. Block Diagram
RY/BY#
V
CC
V
SS
RESET#
Sector Switches
Erase Voltage
Generator
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Chip Enable
Output Enable
Logic
STB
Y-Decoder
Address Latch
X-Decoder
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Input/Output
Buffers
Data
Latch
Y-Gating
Cell Matrix
WE#
BYTE#
CE#
OE#
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V
CC
Detector
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Timer
A0–A20 (A0-A21 Model 00)
Document Number: 002-02003 Rev. *B
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Command
Register
PGM Voltage
Generator
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State
Control
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DQ0
–
DQ15 (A-1), (DQ0-DQ7 Model 00)
Page 4 of 64
S29AL032D
3.
Connection Diagrams
Figure 3.1
40-pin Standard TSOP
Figure 3.2
48-pin Standard TSOP
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE#
RESET#
NC
WP#/ACC
RY/BY#
A18
A17
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
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A16
A15
A14
A13
A12
A11
A9
A8
WE#
RESET#
ACC
RY/BY#
A18
A7
A6
A5
A4
A3
A2
A1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
A17
V
SS
A20
A19
A10
DQ7
DQ6
DQ5
DQ4
V
CC
V
CC
A21
DQ3
DQ2
DQ1
DQ0
OE#
V
SS
CE#
A0
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48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
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A16
BYTE#
V
SS
DQ15/A-1
DQ7
DQ14
DQ6
DQ13
DQ5
DQ12
DQ4
V
CC
DQ11
DQ3
DQ10
DQ2
DQ9
DQ1
DQ8
DQ0
OE#
V
SS
CE#
A0
Document Number: 002-02003 Rev. *B
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Embedded System
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