S29CD016J/S29CL016J
Known Good Die
16 Megabit (512k x 32-Bit) CMOS 2.6 or 3.3 Volt-only
Burst Mode, Dual Boot, Simultaneous Read/Write
Flash Memory with VersatileI/O
™
Supplement
(Preliminary)
General Description
The Spansion S29CD016J and S29CL016J devices are Floating Gate products fabricated in 110 nm process technology.
These burst mode Flash devices are capable of performing simultaneous read and write operations with zero latency on two
separate banks. These products can operate up to 56 MHz and use a single V
CC
of 2.5 V to 2.75 V (S29CD-J) or 3.0 V to 3.6 V
(S29CL-J) that make them ideal for today’s demanding automotive applications.
Distinctive Characteristics
Single 2.6 V (S29CD-J) or 3.3 V (S29CL-J) for read/program/
erase
110 nm Floating Gate Technology
Simultaneous Read/Write operation with zero latency
x32 Data Bus
Dual Boot Sector Configuration (top and bottom)
Flexible Sector Architecture
– CD016J & CL016J: Eight 2K Double word, Thirty-two 16K Double
word, and Eight 2K Double Word sectors
Cycling Endurance: 1,000,000 write cycles per sector
(typical)
Command set compatible with JECEC (JC42.4) standard
Supports Common Flash Interface (CFI)
Persistent and Password methods of Advanced Sector
Protection
Unlock Bypass program command to reduce programming
time
Write operation status bits indicate program and erase
operation completion
Hardware (WP#) protection of two outermost sectors in the
large bank
Ready/Busy (RY/BY#) output indicates data available to
system
Suspend and Resume commands for Program and Erase
Operation
VersatileI/O™ control (1.65 V to V
CC
)
Programmable Burst Interface
– Linear for 2, 4, and 8 double word burst with wrap around
Secured Silicon Sector that can be either factory or customer
locked
20 year data retention (typical)
Performance Characteristics
Read Access Times
Speed Option (MHz)
Max Asynch. Access Time, ns (t
ACC
)
Max Synch. Latency, ns (t
IACC
)
Max Synch. Burst Access, ns (t
BACC
)
Max CE# Access Time, ns (t
CE
)
Max OE# Access time, ns (t
OE
)
56
54
54
8
54
20
40
54
54
8
54
20
Typical Program and Erase Times
Double Word Programming
Sector Erase
18 µs
1.0 s
Current Consumption (Max values)
Continuous Burst Read @ 56 MHz
Program
Erase
Standby Mode
90 mA
50 mA
50 mA
60 µA
Publication Number
S29CD016J-CL016J_KGD_SP
Revision
A
Amendment
3
Issue Date
March 9, 2009
This document states the current technical specifications regarding the Spansion product(s) described herein. The Preliminary status of this document indicates that product qual-
ification has been completed, and that initial production has begun. Due to the phases of the manufacturing process that require maintaining efficiency and quality, this document
may be revised by subsequent versions or modifications due to changes in technical specifications.
Supplement
(Preliminar y)
Table of Contents
General Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Distinctive Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Performance Characteristics
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Table of Contents
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
List of Figures
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
List of Tables
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
S29CD/CL016J Features.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.
2.
3.
4.
5.
Die Photograph.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Die Pad Locations
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pad Description
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Ordering Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
4.1
Valid Combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Packaging Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.1
Surftape Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
5.2
Waffle Pack Packaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Product Test Flow.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Absolute Maximum Ratings
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Operating Ranges
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Physical Specifications
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Manufacturing Information
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Special Handling Instructions.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
11.1 Processing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
11.2 Storage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
DC Characteristics for KGD Devices at 145°C.
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Terms and Conditions of Sale for Spansion Non-Volatile Memory Die.
. . . . . . . . . . . . . . . . . . . . 14
Revision Summary
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
6.
7.
8.
9.
10.
11.
12.
13.
14.
List of Figures
Figure 6.1
Figure 7.1
Figure 7.2
Spansion KGD Product Test Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Maximum Negative Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Maximum Positive Overshoot Waveform . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
List of Tables
Table 3.1
Table 12.1
Pads Relative To Die Center . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
DC Characteristics, CMOS Compatible . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
2
S29CD016J/S29CL016J Known Good Die
Revision A3 March 9, 2009
Supplement
(Pre limina r y)
S29CD/CL016J Features
The S29CD016J & S29CL016J Flash devices are burst mode, dual boot, simultaneous read/write Flash
memories with VersatileI/O™ manufactured on 110 nm process technology.
The S29CD016J is a 16 megabit, 2.6 volt-only, single-power-supply, burst mode Flash memory device that
can be configured for 524,288 double words. The S29CL016J is the 3.3 volt-only version of that device. Both
devices can be programmed in standard EPROM programmers.
To eliminate bus contention, each device has separate chip enable (CE#), write enable (WE#) and output
enable (OE#) controls. Additional control inputs are required for synchronous burst operations: Load Burst
Address Valid (ADV#), and Clock (CLK).
Each device requires only a single 2.6 volt-only (2.50 V – 2.75 V) or 3.3 volt-only (3.00 V – 3.60 V) for both
read and write functions. A 12.0-volt V
PP
is not required for program or erase operations, although an
acceleration pin is available if faster programming performance is required.
The device is entirely command set compatible with the JEDEC single-power-supply Flash standard. The
software command set is compatible with the command sets of the 5 V Am29F and 3 V Am29LV Flash
families. Commands are written to the command register using standard micro-processor write timing.
Register contents serve as inputs to an internal state-machine that controls the erase and programming
circuitry. Write cycles also internally latch addresses and data needed for the programming and erase
operations. Reading data out of the device is similar to reading from other Flash or EPROM devices.
The
Unlock Bypass
mode facilitates faster programming times by requiring only two write cycles to program
data instead of four.
The
Simultaneous Read/Write architecture
provides simultaneous operation by dividing the memory space
into two banks. The device can begin programming or erasing in one bank, and then simultaneously read
from the other bank, with zero latency. This releases the system from waiting for the completion of program or
erase operations.
The device provides a 256-byte
Secured Silicon Sector
with an one-time-programmable (OTP) mechanism.
In addition, the device features several levels of sector protection, which can disable both the program and
erase operations in certain sectors or sector groups:
Persistent Sector Protection
is a command sector
protection method that replaces the old 12 V controlled protection method;
Password Sector Protection
is a
highly sophisticated protection method that requires a password before changes to certain sectors or sector
groups are permitted;
WP# Hardware Protection
prevents program or erase in the two outermost 8 Kbytes
sectors of the larger bank.
The device defaults to the Persistent Sector Protection mode. The customer must then choose if the
Standard or Password Protection method is most desirable. The WP# Hardware Protection feature is always
available, independent of the other protection method chosen.
The
VersatileI/O™ (V
IO
)
feature allows the output voltage generated on the device to be determined based
on the V
ΙΟ
level. This feature allows this device to operate in the 1.8 V I/O environment, driving and receiving
signals to and from other 1.8 V devices on the same bus.
The host system can detect whether a program or erase operation is complete by observing the RY/BY# pin,
by reading the DQ7 (Data# Polling), or DQ6 (toggle)
status bits.
After a program or erase cycle has been
completed, the device is ready to read array data or accept another command.
The
sector erase architecture
allows memory sectors to be erased and reprogrammed without affecting the
data contents of other sectors. The device is fully erased when shipped from the factory.
Hardware data protection
measures include a low V
CC
detector that automatically inhibits write operations
during power transitions. The
password and software sector protection
feature disables both program and
erase operations in any combination of sectors of memory. This can be achieved in-system at V
CC
level.
The
Program/Erase Suspend/Erase Resume
feature enables the user to put erase on hold for any period of
time to read data from, or program data to, any sector that is not selected for erasure. True background erase
can thus be achieved.
The
hardware RESET# pin
terminates any operation in progress and resets the internal state machine to
reading array data.
March 9, 2009 Revision A3
S29CD016J/S29CL016J Known Good Die
3
Supplement
(Preliminar y)
The device offers two power-saving features. When addresses have been stable for a specified amount of
time, the device enters the
automatic sleep mode.
The system can also place the device into the
standby
mode.
Power consumption is greatly reduced in both these modes.
Spansion Flash technology combines years of Flash memory manufacturing experience to produce the
highest levels of quality, reliability and cost effectiveness. The device electrically erases all bits within a sector
simultaneously via Fowler-Nordheim tunnelling. The data is programmed using hot electron injection.
0.0.0.1
Electrical Specifications
Refer to the S29CD-J & S29CL-J Flash Family data sheet, publication number S29CD-J_CL-J_00, for full
electrical specifications on the S29CD032J/S29CL032J in KGD form.
1. Die Photograph
4
S29CD016J/S29CL016J Known Good Die
Revision A3 March 9, 2009
Supplement
(Pre limina r y)
2. Die Pad Locations
30
25
20
15
10
8
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
30
31
6
31
7
5
32
33
34
35
35
36
Y
4
3
5
2
37
1
74
38
X
1
73
39
74
72
40
40
41
42
71
43
70
44
69
45
45
49
46
47
48
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
70
47
50
55
60
65
69
Logo
March 9, 2009 Revision A3
S29CD016J/S29CL016J Known Good Die
5
DSP and ARM Processors
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