DATASHEET
VERY LOW POWER CLOCK FOR FREESCALE MCU’S
IDT5U49319
General Description
The IDT5U49319 is a very low power clock for Freescale
MCU’s. It uses a 1.5V core and Low-Power HCSL
(LP-HCSL) differential outputs for minimal power
consumption. The SATA and SRC outputs are PCIe Gen1/2
compatible.
Features/Benefits
•
Various outputs are configurable to run in power down;
•
•
•
•
•
•
•
•
•
supports Wake_On_LAN
FPGA clock frequency is selectable via SMBus; allows
low-power system standby
Strapping pin sources SRC outputs from either spreading
or non-spreading PLL; maximum system flexibility
FLEX clock is pin selectable to be FPGA clock or USB
PHY clock; maximum system flexibility
TEST pin tri-states all outputs; speeds up board test
External 25MHz crystal; supports tight ppm
OE# pins; support SRC power management
Low power differential clock outputs; reduced power and
board space
Differential outputs internally terminated to 100
differential impedance; reduced board space
Space-saving 7x7mm 48-pin VFQFPN with 0.5mm pad
pitch; reduced board space without the need for fine pitch
assembly techniques
Recommended Application
Clock Chip for Freescale P10xx & P20xx MCU’s
Output Features
•
•
•
•
•
•
•
•
4 - LP-HCSL SRC pairs w/integrated source terminations
1 - LP-HCSL SATA pair w/integrated source terminations
1 - 25MHz 2.5V/3.3V LVCMOS output
2 - 66.66MHz 3.3V LVCMOS outputs
1 - FPGA 33.33MHz 2.5V/3.3V LVCMOS output
1 - FLEX clock 2.5V/3.3V LVCMOS output
1 - 125M GTX clock 2.5V LVCMOS output
1 - 26MHz 2.5V/3.3V LVCMOS output
Key Specifications
•
SRC/SATA cycle-to-cycle jitter <85ps
•
SRC/SATA PCIe Gen1/2 compliant
Block Diagram
25M
25M
vMODE0
PLL A
-0.5%
SS
1
0
3V66(1:0)
FPGACLK
SRC(3:0)_LRS
SATA_LRS
GTX125M
PLL B
non-SS
1
0
PLL C
vMODE1
SDATA_3.3
SCLK_3.3
^CLKPWRGD_PD#_3.3
vSS_EN_1.5
^OE(A:B)#_3.3
vvTEST_SEL_1.5
vFS(1:0)_1.5
Control
Logic
FLEXCLK
26M
IDT®
VERY LOW POWER CLOCK FOR FREESCALE MCU’S
1
IDT5U49319
REV D 043014
IDT5U49319
VERY LOW POWER CLOCK FOR FREESCALE MCU’S
Pin Configuration
^CKPWRGD_PD#_3.3
VDD_CORE_1.5
SATA#_LRS
SRC3#_LRS
GND_CORE
SATA_LRS
SRC3_LRS
GNDXTAL
48 47 46
45 44 43 42 41 40 39 38
37
X1_25
VDDXTAL_3.3
VDDO2.5_3.3
REF_25
SDATA_3.3
SCLK_3.3
VDDO3.3
3V66_0
3V66_1
GND3V66
GNDFPGA
VDDO2.5_3.3
1
2
3
4
5
6
7
8
9
10
11
12
VDDO2.5_3.3
GNDFLEX
FPGACLK
36
35
34
33
32
31
30
29
28
27
26
25
VDD_CORE_1.5
GND125
GND_CORE
vvTEST_SEL_1.5
GND_CORE
SRC2#_LRS
SRC2_LRS
SRC1#_LRS
SRC1_LRS
OEA#_3.3
VDD_CORE_1.5
SRC0#_LRS
SRC0_LRS
GNDSRC
vSS_EN_1.5_LAT
5U49319
NLG48 package
13 14 15 16 17 18 19 20 21 22 23 24
vMODE0/26M
VDDO2.5_3.3
VDDO2.5
GND26
vMODE1/FLEXCLK
GTX125M
48-pin VFQFPN, 7X7 mm, 0.5mm pitch
v prefix indicates internal 120KOhm pull down resistor
vv prefix indicates internal 60KOhm pull down resistor
^ prefix indicates internal 120KOhm pull up resistor
Color coding indicates the power domains in the device.
NOTE: ePAD is not electrically connected to the die and should be soldered to PCB Ground plane for
specifed thermal performance
Singled-ended Output Power Management Table
CKPWRGD_
PD#_3.3
1
1
0
0
X
SMBus
OE bit
Enable
Enable
Enable
Enable
Disable
SMBus
PD# Run bit
1
0
1
0
X
REF_25
Running
Running
Running
Low
Low
3V66_(1:0)
Running
Running
Running
Low
Low
FPGACLK
Running
Running
Running
Low
Low
GTX125M
Running
Running
Running
Low
Low
SRC Power Management Table
CKPWRGD_
SMBus
PD#_3.3
Register OE
OEA#_3.3
SRC(1:0)_LRS
OEB#_3.3
SRC(3:2)_LRS
True/Comp
True/Comp
1
Enable
0
Running
0
Running
1
Enable
1
Low/Low
1
Low/Low
Enable
X
Low/Low
X
Low/Low
0
X
X
Low/Low
X
Low/Low
Disable
Note: OEA#_3.3 controls SRC(1:0)_LRS. OEB#_3.3 controls SRC(3:2)_LRS.
SATA Power Management Table
CKPWRGD_
SMBus
PD#_3.3
Register OE
1
Enable
Enable
0
X
Disable
SATA_LRS
True/Comp
Running
Low/Low
Low/Low
2
IDT5U49319
REV D 043014
IDT®
VERY LOW POWER CLOCK FOR FREESCALE MCU’S
OEB#_3.3
vFS1_1.5
vFS0_1.5
X2
IDT5U49319
VERY LOW POWER CLOCK FOR FREESCALE MCU’S
Singled-ended Latched I/O and I/O Power
Management Table
CKPWRGD_
SMBus
SMBus
FLEXCLK
26M
PD#_3.3
Register OE PD# Run bit
1
Enable
Running
Running
1
1
Enable
Running
Running
0
1
Disable
Low
Low
X
Enable
1
Running
Running
0
Enable
0
0
Hi-Z
Hi-Z
Disable
1
0
Low
Low
Disable
0
0
Hi-Z
Hi-Z
Note: After power is applied and
before
CKPWRGD_PD#_3.3 is
asserted, these outputs are Hi-Z to allow for any pull up or pull down to
be latched on the first high assertion of CKPWRGD_PD#_3.3.
vMODE1 Defintion Table
vMODE1
0
0
0
0
1
1
1
1
vFS1_1.5 vFS0_1.5
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
FLEXCLK
FLEXCLK
Source
Frequency (MHz)
PLL C
PLL C
PLL C
PLL C
PLL A
PLL A
PLL A
PLL A
30.00
48.00
24.00
12.00
33.33
16.67
8.33
4.17
FPGACLK Frequency Select Table
Power Connections
Pin Number
VDD
GND
2
47
3
47
7
10
12
11
14
15
19
18
20
22
23
24
29
26
29
35
40
43
Description
XTAL OSC Circuit, SMBus
REF_25 Output
3V66 ouputs and logic
FPGACLK output and logic
FLEXCLK output and logic
26M output and logic
GTX125M output and logic
PLL C Analog
SRC Outputs
PLL A Analog
PLL B Analog and SATA
FPGA
FS1
(B0b3)
0
0
1
1
FPGA
FS0
(B0b2)
0
1
0
1
FPGACLK
Frequency
(MHz)
33.33
16.67
8.33
4.17
PLL A Spread Enable/Selection Table
SS1
vSS_EN_1.5
1
(B4b0)
(B4b2)
0
1
1
1
1
NOTES:
1. Default for SS(1:0) is 00
2. Only applies to SRC(3:0)_LRS if vMODE0 = 1
X
0
0
1
1
SS0
(B4b1)
X
0
1
0
1
1
SPREAD
OFF
-0.50%
-0.40%
-0.30%
0.00%
vMODE0 Definition Table
vMODE0
0
1
SRC(3:0)_LRS
Source
Non-spread
PLL B
Spread-Capable
PLL A
IDT®
VERY LOW POWER CLOCK FOR FREESCALE MCU’S
3
IDT5U49319
REV D 043014
IDT5U49319
VERY LOW POWER CLOCK FOR FREESCALE MCU’S
Pin Descriptions
Num.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
Pin Name
X1_25
VDDXTAL_3.3
VDDO2.5_3.3
REF_25
SDATA_3.3
SCLK_3.3
VDDO3.3
3V66_0
3V66_1
GND3V66
GNDFPGA
VDDO2.5_3.3
FPGACLK
VDDO2.5_3.3
GNDFLEX
vMODE1/FLEXCLK
vMODE0/26M
GND26
VDDO2.5_3.3
VDDO2.5
GTX125M
GND125
VDD_CORE_1.5
GND_CORE
vSS_EN_1.5_LAT
GNDSRC
SRC0_LRS
SRC0#_LRS
VDD_CORE_1.5
OEA#_3.3
SRC1_LRS
SRC1#_LRS
SRC2_LRS
SRC2#_LRS
GND_CORE
vvTEST_SEL_1.5
OEB#_3.3
SRC3#_LRS
Type
IN
PWR
PWR
OUT
I/O
IN
PWR
OUT
OUT
GND
GND
PWR
OUT
PWR
GND
LATCHED
I/O
LATCHED
I/O
GND
PWR
PWR
OUT
GND
PWR
GND
LATCHED
IN
GND
Description
Crystal input, Nominally 25.00MHz.
Power supply for XTAL, nominal 3.3V
Power supply for outputs, either 2.5V or 3.3V.
25 MHz reference clock.
Data pin for SMBus circuitry, 3.3V tolerant.
Clock pin of SMBus circuitry, 3.3V tolerant.
Power supply for outputs,nominal 3.3V.
3.3V 66.66MHz clock output
3.3V 66.66MHz clock output
Ground pin for the 3.3V 66MHz clocks
Ground pin for the FPGA clock output.
Power supply for outputs, either 2.5V or 3.3V.
FPGA clock output. See frequency tables for values.
Power supply for outputs, either 2.5V or 3.3V.
Ground pin for the FLEX clock output.
Mode Select Pin/FLEX clock output. This pin has an internal pull-down and is latched
on the first power up of the device.
Mode Select Pin/26MHz output. This pin has an internal pull-down and is latched on the
first power up of the device.
Ground pin for the 26MHz output.
Power supply for outputs, either 2.5V or 3.3V.
Power supply for outputs, nominally 2.5V.
125MHz output
Ground pin for 125M output
Power for PLL core components requiring 1.5V
Ground pin for the PLL core.
1.5V LVCMOS latched input to select spread spectrum amount:
1 = -0.5% spread, 0 = Spread Off
Ground pin for the SRC outputs
True clock of LP-HCSL SRC clock with integrated source termination. See Differential
OUT
Test Load for output impedance.
Complementary clock of LP-HCSL SRC clock with integrated source termination. See
OUT
Differential Test Load for output impedance.
PWR
Power for PLL core components requiring 1.5V
Active low input 3.3V tolerant for enabling output bank A.
IN
1 =disable output, 0 = enable output
True clock of LP-HCSL SRC clock with integrated source termination. See Differential
OUT
Test Load for output impedance.
Complementary clock of LP-HCSL SRC clock with integrated source termination. See
OUT
Differential Test Load for output impedance.
True clock of LP-HCSL SRC clock with integrated source termination. See Differential
OUT
Test Load for output impedance.
Complementary clock of LP-HCSL SRC clock with integrated source termination. See
OUT
Differential Test Load for output impedance.
GND
Ground pin for the PLL core.
TEST_SEL: latched input to select TEST MODE. Max input voltage is 1.5V
LATCHED
1 = All outputs are tri-stated for test
IN
0 = All outputs behave normally.
Active low input 3.3V tolerant for enabling output bank B.
IN
1 =disable output, 0 = enable output
Complementary clock of LP-HCSL SRC clock with integrated source termination. See
OUT
Differential Test Load for output impedance.
IDT®
VERY LOW POWER CLOCK FOR FREESCALE MCU’S
4
IDT5U49319
REV D 043014
IDT5U49319
VERY LOW POWER CLOCK FOR FREESCALE MCU’S
Pin Descriptions (cont.)
Num.
39
40
41
42
43
44
45
46
47
48
Pin Name
SRC3_LRS
VDD_CORE_1.5
SATA_LRS
SATA#_LRS
GND_CORE
vFS0_1.5
vFS1_1.5
^CKPWRGD_PD#_3.3
GNDXTAL
X2
Description
True clock of LP-HCSL SRC clock with integrated source termination. See Differential
OUT
Test Load for output impedance.
PWR
Power for PLL core components requiring 1.5V
True clock of LP-HCSL SATA clock with integrated source termination. See Differential
OUT
Test Load for output impedance.
Complementary clock of LP-HCSL SATA clock with integrated source termination. See
OUT
Differential Test Load for output impedance.
GND
Ground pin for the PLL core.
LATCHED 1.5V latched input pin for frequency selection. See Frequency Select Tables for Details.
IN
This pin has an internal pull down.
LATCHED 1.5V latched input pin for frequency selection. See Frequency Select Tables for Details.
IN
This pin has an internal pull down.
Input notifies device to sample latched inputs and start up on first high assertion. Low
IN
enters Power Down Mode, subsequent high assertions exit Power Down Mode. This pin
has internal pull-up resistor and is 3.3V tolerant.
GND
GND for XTAL
OUT
Crystal output.
Type
IDT®
VERY LOW POWER CLOCK FOR FREESCALE MCU’S
5
IDT5U49319
REV D 043014
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