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79RC64V474-180DZ9

Description
RISC Microprocessor, 64-Bit, 180MHz, PQFP128, QFP-128
CategoryThe embedded processor and controller    Microcontrollers and processors   
File Size921KB,25 Pages
ManufacturerIDT (Integrated Device Technology)
Download Datasheet Parametric View All

79RC64V474-180DZ9 Overview

RISC Microprocessor, 64-Bit, 180MHz, PQFP128, QFP-128

79RC64V474-180DZ9 Parametric

Parameter NameAttribute value
Is it lead-free?Contains lead
Is it Rohs certified?incompatible
MakerIDT (Integrated Device Technology)
Parts packaging codeQFP
package instructionQFP-128
Contacts128
Reach Compliance Codecompliant
ECCN code3A001.A.3
Address bus width32
bit size64
boundary scanYES
maximum clock frequency90 MHz
External data bus width32
FormatFLOATING POINT
Integrated cacheYES
JESD-30 codeS-PQFP-G128
JESD-609 codee0
length28 mm
low power modeYES
Number of terminals128
Maximum operating temperature85 °C
Minimum operating temperature
Package body materialPLASTIC/EPOXY
encapsulated codeQFP
Package shapeSQUARE
Package formFLATPACK
Peak Reflow Temperature (Celsius)225
Certification statusNot Qualified
Maximum seat height4.1 mm
speed180 MHz
Maximum supply voltage3.63 V
Minimum supply voltage2.97 V
Nominal supply voltage3.3 V
surface mountYES
technologyCMOS
Temperature levelOTHER
Terminal surfaceTin/Lead (Sn/Pb)
Terminal formGULL WING
Terminal pitch0.8 mm
Terminal locationQUAD
Maximum time at peak reflow temperature20
width28 mm
uPs/uCs/peripheral integrated circuit typeMICROPROCESSOR, RISC
RISController
TM
Embedded
64-bit Microprocessor, based on
RISCore4000
TM
x
RC64474
RC64475
x
High performance 64-bit microprocessor, based on the
RISCore4000
– Minimized branch and load delays, through streamlined
5-stage scalar pipeline.
– Single and double precision floating-point unit
– 125 peak MFLOP/s at 250 MHz
– 330 Dhrystone MIPS at 250 MHz
– Flexible RC4700-compatible MMU
– Joint TLB on-chip, for virtual-to-physical address mapping
x
On-chip two-way set associative caches
– 16KB instruction cache (I-cache)
– 16KB data cache (D-cache)
x
Optional I-cache and D-cache locking (per set), provides
improved real-time support
x
Enhanced, flexible bus interface allows simple, low-cost
design
– 64-bit Bus Interface option, 1000MB/s bandwidth support
– 32-bit Bus Interface option, 500MB/s bandwidth support
– SDRAM timing protocol, through delayed data in write cycles
– RC4000/RC5000 family bus-protocol compatibility
– Bus runs at fraction of pipeline clock (1/2 to 1/8)
x
Implements MIPS-III Instruction Set Architecture (ISA)
x
3.3V core with 3.3V I/O
Software compatible with entire RISController Series of
Embedded Microprocessors
x
Industrial temperature range support
x
Active power management
– Powers down inactive units, through sleep-mode feature
x
100% pin compatibility between RC64574, RC64474 and
RC4640
x
100% pin compatibility between RC64575, RC64475 and
RC4650
x
RC64474 available in 128-pin QFP package, for 32-bit only
systems
x
RC64475 available in 208-pin QFP package, for full 64/32 bit
systems
x
Simplified board-level testing, through full Joint Test Action
Group (JTAG) boundary scan
x
Windows® CE compliant
The IDT logo is a registered trademark and RC32134, RC32364, RC64145, RC64474, RC64475, RC4650, RC4640, RC4600,RC4700 RC3081, RC3052, RC3051, RC3041, RISController, and RISCore are trade-
marks of Integrated Device Technology, Inc.
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330 MIPS
64-bit
RISCore4000
CPU Core
System Control
Coprocessor
(CPO)
125 MFLOPS
Single/Double
Precision
FPA
Control B us
Data B us
Instruction Bus
16KB
Instruction Cache
(Lockable)
32-/64-bit
Synchronized
System
Interface
16KB
Data Cache
(Lockable)
1 of 25
©
1999 Integrated Device Technology, Inc.
April 17, 2000
DSC 4952
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