853001AMT datasheet, PDF - EEWORLD Datasheet

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853001AMT: DescriptionLow Skew Clock Driver, 853001 Series, 1 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, MS-012, SOIC-8; Categorylogic logic; File Size215KB，17 Pages; ManufacturerIDT (Integrated Device Technology)

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853001AMT Overview

Low Skew Clock Driver, 853001 Series, 1 True Output(s), 0 Inverted Output(s), PDSO8, 3.90 X 4.90 MM, 1.37 MM HEIGHT, MS-012, SOIC-8

853001AMT Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	SOIC
package instruction	SOP, SOP8,.25
Contacts	8
Reach Compliance Code	not_compliant
Other features	ECL MODE: VCC = 0V WITH VEE = -2.375V TO -5.25V
series	853001
Input adjustment	DIFFERENTIAL
JESD-30 code	R-PDSO-G8
JESD-609 code	e0
length	4.9 mm
Logic integrated circuit type	LOW SKEW CLOCK DRIVER
Humidity sensitivity level	1
Number of functions	1
Number of inverted outputs
Number of terminals	8
Actual output times	1
Maximum operating temperature	85 °C
Minimum operating temperature	-40 °C
Package body material	PLASTIC/EPOXY
encapsulated code	SOP
Encapsulate equivalent code	SOP8,.25
Package shape	RECTANGULAR
Package form	SMALL OUTLINE
Peak Reflow Temperature (Celsius)	240
power supply	+-2.5/+-5 V
Prop。Delay @ Nom-Sup	0.5 ns
propagation delay (tpd)	0.5 ns
Certification status	Not Qualified
Maximum seat height	1.75 mm
Maximum supply voltage (Vsup)	5.25 V
Minimum supply voltage (Vsup)	2.375 V
Nominal supply voltage (Vsup)	3.3 V
surface mount	YES
Temperature level	INDUSTRIAL
Terminal surface	Tin/Lead (Sn85Pb15)
Terminal form	GULL WING
Terminal pitch	1.27 mm
Terminal location	DUAL
Maximum time at peak reflow temperature	30
width	3.9 mm

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ICS853001

1:1, D

IFFERENTIAL

LVPECL-

2.5V, 3.3V, 5V LVPECL/ECL B

UFFER

ENERAL

ESCRIPTION

The ICS853001 is a 1:1 Differential LVPECL-

to-LVPE C L B u f fe r a n d a m e m b e r o f t h e

HiPerClockS™

HiPerClock S ™ family of High Perfor mance

Clock Solutions from IDT. The ICS853001

may be used to regenerate LVPECL clocks which

may have been attenuated, across a long trace, or may also

be used as a differential-to-LVPECL translator. The differen-

tial input can accept the following differential input types:

LVPECL, LVDS and CML. The device also has an output en-

able pin for debug/test purposes. When the output is disabled,

it drives differential LOW (Q = LOW, nQ = HIGH). The

ICS853001 is packaged in either a 3mm x 3mm 8-pin TSSOP

or 3.9mm x 4.9mm 8-pin SOIC, making it ideal for use on

space-constrained boards.

EATURES

•

1:1 Differential LVPECL-to-LVPECL / ECL buffer

•

One LVPECL clock output pair

•

One Differential LVPECL PCLK, nPCLK input pair

•

PCLK, nPCLK pair can accept the following

differential input levels: LVPECL, LVDS, CML

•

Maximum output frequency: >2.5GHz

•

Part-to-part skew: 100ps (maximum)

•

Propagation delay: 500ps (maximum)

•

Additive phase jitter, RMS: 0.03ps (typical)

•

LVPECL mode operating voltage supply range:

= 2.375V to 5.25V, V

= 0V

•

ECL mode operating voltage supply range:

= 0V, V

= -5.25V to -2.375V

•

-40°C to 85°C ambient operating temperature

•

Available in both standard (RoHS5) and lead-free (RoHS 6)

packages

LOCK

IAGRAM

SSIGNMENT

D Q

PCLK

nPCLK

PCLK

nPCLK

ICS853001

8-Lead TSSOP, 118 mil

3mm x 3mm x 0.95mm package body

G Package

Top View

ICS853001

8-Lead SOIC

3.90mm x 4.90mm x 1.37mm package body

M Package

Top View

853001AG

REV. A NOVEMBER 24, 2008

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