89HPES12NT3ZABC datasheet, PDF

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89HPES12NT3ZABC: DescriptionPCI Bus Controller, PBGA324, 19 X 19 MM, 1 MM PITCH, BGA-324; CategoryThe embedded processor and controller Microcontrollers and processors; File Size252KB，29 Pages; ManufacturerIDT (Integrated Device Technology)

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89HPES12NT3ZABC Overview

PCI Bus Controller, PBGA324, 19 X 19 MM, 1 MM PITCH, BGA-324

89HPES12NT3ZABC Parametric

Parameter Name	Attribute value
Is it lead-free?	Contains lead
Is it Rohs certified?	incompatible
Maker	IDT (Integrated Device Technology)
Parts packaging code	BGA
package instruction	19 X 19 MM, 1 MM PITCH, BGA-324
Contacts	324
Reach Compliance Code	not_compliant
ECCN code	3A001.A.3
Address bus width
Bus compatibility	PCI
maximum clock frequency	125 MHz
External data bus width
JESD-30 code	S-PBGA-B324
JESD-609 code	e0
length	19 mm
Humidity sensitivity level	3
Number of terminals	324
Maximum operating temperature	70 °C
Minimum operating temperature
Package body material	PLASTIC/EPOXY
encapsulated code	LBGA
Encapsulate equivalent code	BGA324,18X18,40
Package shape	SQUARE
Package form	GRID ARRAY, LOW PROFILE
Peak Reflow Temperature (Celsius)	225
power supply	1,3.3 V
Certification status	Not Qualified
Maximum seat height	1.5 mm
Maximum supply voltage	1.1 V
Minimum supply voltage	0.9 V
Nominal supply voltage	1 V
surface mount	YES
technology	CMOS
Temperature level	COMMERCIAL
Terminal surface	Tin/Lead (Sn63Pb37)
Terminal form	BALL
Terminal pitch	1 mm
Terminal location	BOTTOM
Maximum time at peak reflow temperature	20
width	19 mm
uPs/uCs/peripheral integrated circuit type	BUS CONTROLLER, PCI

89HPES12NT3ZABC Preview

12-lane 3-Port Non-Transparent

PCI Express® Switch

89HPES12NT3

Data Sheet

Preliminary Information*

Device Overview

The 89HPES12NT3 is a member of the IDT PRECISE™ family of

PCI Express® switching solutions offering the next-generation I/O inter-

connect standard. The PES12NT3 is a 12-lane, 3-port peripheral chip

that performs PCI Express Base switching with a feature set optimized

for high performance applications such as servers, storage, and commu-

nications/networking. It provides high-performance I/O connectivity and

switching functions between a PCIe® upstream port, a transparent

downstream port, and a non-transparent downstream port.

With non-transparent bridging (NTB) functionality, the PES12NT3

can be used standalone or as a chipset with IDT PCIe System Intercon-

nect Switches in multi-host and intelligent I/O applications such as

communications, storage, and blade servers where inter-domain

communication is required.

Features

◆

High Performance PCI Express Switch

–

Twelve PCI Express lanes (2.5Gbps), three switch ports

–

Delivers 48 Gbps (6 GBps) of aggregate switching capacity

–

Low latency cut-through switch architecture

–

Support for Max Payload size up to 2048 bytes

–

Supports one virtual channel and eight traffic classes

–

PCI Express Base specification Revision 1.0a compliant

Flexible Architecture with Numerous Configuration Options

–

Port arbitration schemes utilizing round robin

–

Supports automatic per port link width negotiation (x4, x2, or

x1)

–

Static lane reversal on all ports

–

Automatic polarity inversion on all lanes

–

Supports locked transactions, allowing use with legacy soft-

ware

–

Ability to load device configuration from serial EEPROM

–

Ability to control device via SMBus

◆

Non-Transparent Port

–

Crosslink support on NTB port

–

Four mapping windows supported

•

Each may be configured as a 32-bit memory or I/O window

•

May be paired to form a 64-bit memory window

–

Interprocessor communication

•

Thirty-two inbound and outbound doorbells

•

Four inbound and outbound message registers

•

Two shared scratchpad registers

–

Allows up to sixteen masters to communicate through the non-

transparent port

–

No limit on the number of supported outstanding transactions

through the non-transparent bridge

–

Completely symmetric non-transparent bridge operation

allows similar/same configuration software to be run

–

Supports direct connection to a transparent or non-transparent

port of another switch

◆

Block Diagram

3-Port Switch Core

Frame Buffer

Route Table

Port

Arbitration

Scheduler

Transaction Layer

Data Link Layer

Transaction Layer

Data Link Layer

Transaction Layer

Data Link Layer

Non-

Transparent

Bridge

Multiplexer / Demultiplexer

Phy

Logical

Layer

Phy

Logical

Layer

Phy

Logical

Layer

Multiplexer / Demultiplexer

Phy

Logical

Layer

Phy

Logical

Layer

Phy

Logical

Layer

Multiplexer / Demultiplexer

Phy

Logical

Layer

Phy

Logical

Layer

Phy

Logical

Layer

...

SerDes

12 PCI Express Lanes

x4 Upstream Port and Two x4 Downstream Ports

Figure 1 Internal Block Diagram

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

Inc.

1 of 29

2007 Integrated Device Technology, Inc.

*Notice: The information in this document is subject to change without notice

April 11, 2007

DSC 6929

IDT 89HPES12NT3 Data Sheet

Highly Integrated Solution

–

Requires no external components

–

Incorporates on-chip internal memory for packet buffering and

queueing

–

Integrates twelve 2.5 Gbps embedded full duplex SerDes,

8B/10B encoder/decoder (no separate transceivers needed)

◆

Reliability, Availability, and Serviceability (RAS) Features

–

Upstream port can be dynamically swapped with non-trans-

parent downstream port to support failover applications

–

Internal end-to-end parity protection on all TLPs ensures data

integrity even in systems that do not implement end-to-end

CRC (ECRC)

–

Supports ECRC pass-through in transparent and non-trans-

parent ports

–

Supports Hot-Swap

◆

Power Management

–

Supports PCI Power Management Interface specification,

Revision 1.1 (PCI-PM)

–

Unused SerDes are disabled

◆

Testability and Debug Features

–

Built in SerDes Pseudo-Random Bit Stream (PRBS) generator

–

Ability to read and write any internal register via the SMBus

–

Ability to bypass link training and force any link into any mode

–

Provides statistics and performance counters

◆

Two SMBus Interfaces

–

Slave interface provides full access to all software-visible

registers by an external SMBus master

–

Master interface provides connection for an optional serial

EEPROM used for initialization

–

Master interface is also used by an external Hot-Plug I/O

expander

–

Master and slave interfaces may be tied together so the switch

can act as both master and slave

◆

Eight General Purpose Input/Output pins

◆

Packaged in 19x19mm 324-ball BGA with 1mm ball spacing

◆

management. This includes round robin port arbitration, guaranteeing

bandwidth allocation and/or latency for critical traffic classes in applica-

tions such as high throughput 10 GbE I/Os, SATA controllers, and Fibre

Channel HBAs.

Switch Configuration

The PES12NT3 is a three port switch that contains 12 PCI Express

lanes. Each of the three ports is statically allocated 4 lanes with ports

labeled as A, B and C. Port A is the upstream port, port B is the trans-

parent downstream port, and port C is the non-transparent downstream

port.

During link training, link width is automatically negotiated. Each

PES12NT3 port is capable of independently negotiating to a x4, x2 or x1

width. Thus, the PES12NT3 may be used in virtually any three port

switch configuration (e.g., {x4, x4, x4}, {x4, x2, x2}, {x4, x2, x1}, etc.).

The PES12NT3 supports static lane reversal. For example, lane

reversal for upstream port A may be configured by asserting the PCI

Express Port A Lane Reverse (PEALREV) input signal or through serial

EEPROM or SMBus initialization. Lane reversal for ports B and C may

be enabled via a configuration space register, serial EEPROM, or the

SMBus.

Product Description

Utilizing standard PCI Express interconnect, the PES12NT3 provides

the most efficient high-performance I/O connectivity solution for applica-

tions requiring high throughput, low latency, and simple board layout

with a minimum number of board layers. With support for non-trans-

parent bridging, the PES12NT3, as a standalone switch or as a chipset

with IDT PCIe System Interconnect Switches, enables multi-host and

intelligent I/O applications requiring inter-domain communication. The

PES12NT3 provides 48 Gbps (6 GBps) of aggregated, full-duplex

switching capacity through 12 integrated serial lanes, using proven and

robust IDT technology. Each lane provides 2.5 Gbps of bandwidth in

both directions and is fully compliant with PCI Express Base specifica-

tion 1.0a.

The PES12NT3 is based on a flexible and efficient layered architec-

ture. The PCI Express layer consists of SerDes, Physical, Data Link and

Transaction layers in compliance with PCI Express Base specification

Revision 1.0a. The PES12NT3 can operate either as a store and

forward or cut-through switch depending on the packet size and is

designed to switch memory and I/O transactions. It supports eight Traffic

Classes (TCs) and one Virtual Channel (VC) with sophisticated resource

2 of 29

*Notice: The information in this document is subject to change without notice

April 11, 2007

IDT 89HPES12NT3 Data Sheet

CPU

PES12NT3

CPU

PES12NT3

CPU

PES12NT3

PCIe System Interconnect Switch

Embedded

CPU

Embedded

CPU

SATA / SAS

Embedded

CPU

GbE / 10GigE

Figure 2 PCIe System Interconnect Architecture Block Diagram

Controller 1

CPU

Controller 2

CPU

PES12N3

Cache Maint. &

Possible Data Flow

x4 PCIe

PES12N3

x4 PCIe

Controller

Storage

To Server

FC 2Gb/s and

4Gb/s

FC 2Gb/s and

4Gb/s

To Server

Figure 3 Dual Host Storage System

3 of 29

April 11, 2007

IDT 89HPES12NT3 Data Sheet

Pin Description

The following tables list the functions of the pins provided on the PES12NT3. Some of the functions listed may be multiplexed onto the same pin.

The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero (low)

level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.

Signal

PEALREV

Type

Name/Description

PCI Express Port A Lane Reverse.

When this bit is asserted, the lanes of

PCI Express Port A are reversed. This value may be overridden by modify-

ing the value of the PALREV bit in the PA_SWCTL register.

PCI Express Port A Serial Data Receive.

Differential PCI Express receive

pairs for port A.

PCI Express Port A Serial Data Transmit.

Differential PCI Express trans-

mit pairs for port A

PCI Express Port B Lane Reverse.

When this bit is asserted, the lanes of

PCI Express Port B are reversed. This value may be overridden by modify-

ing the value of the PBLREV bit in the PA_SWCTL register.

PCI Express Port B Serial Data Receive.

Differential PCI Express receive

pairs for port B.

PCI Express Port B Serial Data Transmit.

Differential PCI Express trans-

mit pairs for port B

PCI Express Port C Lane Reverse.

When this bit is asserted, the lanes of

PCI Express Port C are reversed. This value may be overridden by modify-

ing the value of the PCLREV bit in the PA_SWCTL register.

PCI Express Port C Serial Data Receive.

Differential PCI Express receive

pairs for port C.

PCI Express Port C Serial Data Transmit.

Differential PCI Express trans-

mit pairs for port C

PCI Express Reference Clock.

Differential reference clock pair input. This

clock is used as the reference clock by on-chip PLLs to generate the clocks

required for the system logic and on-chip SerDes. The frequency of the dif-

ferential reference clock is determined by the REFCLKM signal.

PCI Express Reference Clock Mode Select.

These signals select the fre-

quency of the reference clock input.

0x0 - 100 MHz

0x1 - 125 MHz

Table 1 PCI Express Interface Pins

PEARP[3:0]

PEARN[3:0]

PEATP[3:0]

PEATN[3:0]

PEBLREV

PEBRP[3:0]

PEBRN[3:0]

PEBTP[3:0]

PEBTN[3:0]

PECLREV

PECRP[3:0]

PECRN[3:0]

PECTP[3:0]

PECTN[3:0]

PEREFCLKP[1:0]

PEREFCLKN[1:0]

REFCLKM

Signal

MSMBADDR[4:1]

MSMBCLK

Type

I/O

Name/Description

Master SMBus Address.

These pins determine the SMBus address of the

serial EEPROM from which configuration information is loaded.

Master SMBus Clock.

This bidirectional signal is used to synchronize

transfers on the master SMBus. It is active and generating the clock only

when the EEPROM or I/O Expanders are being accessed.

Master SMBus Data.

This bidirectional signal is used for data on the mas-

ter SMBus.

Table 2 SMBus Interface Pins (Part 1 of 2)

MSMBDAT

I/O

4 of 29

April 11, 2007

IDT 89HPES12NT3 Data Sheet

Signal

SSMBADDR[5,3:1]

SSMBCLK

SSMBDAT

Type

I/O

Name/Description

Slave SMBus Address.

These pins determine the SMBus address to

which the slave SMBus interface responds.

Slave SMBus Clock.

This bidirectional signal is used to synchronize trans-

fers on the slave SMBus.

Slave SMBus Data.

This bidirectional signal is used for data on the slave

SMBus.

Table 2 SMBus Interface Pins (Part 2 of 2)

Signal

GPIO[0]

Type

I/O

Name/Description

General Purpose I/O.